{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:11:47Z","timestamp":1729627907676,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/isvdat.2015.7208053","type":"proceedings-article","created":{"date-parts":[[2015,8,20]],"date-time":"2015-08-20T21:53:11Z","timestamp":1440107591000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["On logic depth per pipelining stage with power aware flop, wave and hybrid pipelining with gate size and area constraints"],"prefix":"10.1109","author":[{"given":"Priyankar","family":"Talukdar","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ETC.1989.36234"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/92.711317"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0292-0_23"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1287\/opre.1050.0254"},{"article-title":"Intel architecture update","year":"0","author":"horan","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2013.159"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"473","DOI":"10.1109\/4.126534","article-title":"Low-power cmos digital design","volume":"27","author":"chandrakasan","year":"1992","journal-title":"Solid-State Circuits IEEE Journal of"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2004.1349339"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2483028.2483061"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1109\/ISCA.2002.1003558","article-title":"The optimal logic depth per pipeline stage is 6 to 8 fo4 inverter delays","author":"hrishikesh","year":"2002","journal-title":"Computer Architecture 2002 Proceedings 29th Annual International Symposium on"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"7","DOI":"10.1109\/ISCA.2002.1003557","article-title":"The optimum pipeline depth for a microprocessor","author":"hartstein","year":"2002","journal-title":"Computer Architecture 2002 Proceedings 29th Annual International Symposium on"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.52187"}],"event":{"name":"2015 19th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2015,6,26]]},"location":"Ahmedabad, India","end":{"date-parts":[[2015,6,29]]}},"container-title":["2015 19th International Symposium on VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7166536\/7208044\/07208053.pdf?arnumber=7208053","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T18:01:44Z","timestamp":1498240904000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7208053\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/isvdat.2015.7208053","relation":{},"subject":[],"published":{"date-parts":[[2015,6]]}}}