{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:38:02Z","timestamp":1729629482824,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/isvdat.2015.7208074","type":"proceedings-article","created":{"date-parts":[[2015,8,20]],"date-time":"2015-08-20T21:53:11Z","timestamp":1440107591000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["Implementation of high speed radix-10 parallel multiplier using Verilog"],"prefix":"10.1109","author":[{"given":"Sonam","family":"Negi","sequence":"first","affiliation":[]},{"given":"Pitchaiah","family":"Madduri","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.167"},{"key":"ref11","article-title":"Radix-10 Parallel Decimal Multiplier","volume":"1","author":"ingle","year":"2012","journal-title":"International Journal of Electronic Signals and Systems"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.129"},{"key":"ref13","first-page":"47","article-title":"Conditional Speculative Decimal Addition","author":"vazquez","year":"2006","journal-title":"Proc Seventh Conf Real Numbers and Computers (RNC 7)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4542181"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2006.354758"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2005.15"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.1067"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"195","DOI":"10.1109\/ARITH.2007.6","article-title":"A New Family of High-Performance Parallel Decimal Multipliers","author":"vazquez","year":"2007","journal-title":"18th IEEE Symposium on Computer Arithmetic"},{"key":"ref7","first-page":"348","article-title":"Decimal Multiplication Via Carry-Save Addition","author":"schulte","year":"2003","journal-title":"In IEEE International Conference on Applications-Specific Systems Architectures and Processors"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/988952.989040"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2001.987708"},{"key":"ref9","article-title":"VLSI Design of Combined Binary\/Decimal Multioperand Adders","author":"vazquez","year":"2010","journal-title":"INRIA Research Report"}],"event":{"name":"2015 19th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2015,6,26]]},"location":"Ahmedabad, India","end":{"date-parts":[[2015,6,29]]}},"container-title":["2015 19th International Symposium on VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7166536\/7208044\/07208074.pdf?arnumber=7208074","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T18:01:45Z","timestamp":1498240905000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7208074\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/isvdat.2015.7208074","relation":{},"subject":[],"published":{"date-parts":[[2015,6]]}}}