{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T16:54:54Z","timestamp":1729616094795,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/isvdat.2015.7208097","type":"proceedings-article","created":{"date-parts":[[2015,8,20]],"date-time":"2015-08-20T17:53:11Z","timestamp":1440093191000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Analysis of stability and different speed boosting assist techniques towards the design and optimization of high speed SRAM cell"],"prefix":"10.1109","author":[{"given":"Rohan","family":"Sinha","sequence":"first","affiliation":[]},{"given":"Pranay","family":"Samanta","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2004.1356657"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"journal-title":"Digital Integrated Circuits A Design Perspective","year":"0","author":"rabaey","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.913744"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"2577","DOI":"10.1109\/JSSC.2006.883344","article-title":"Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies","volume":"41","author":"jun","year":"2006","journal-title":"IEEE J Solid-State Circuits"},{"journal-title":"Design of Analog CMOS Integrated Circuits","year":"2001","author":"razavi","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2011.5783112"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2005.1497065"},{"key":"ref1","first-page":"55","article-title":"SRAM Leakage Suppression by Minimizing Standby Supply Voltage","author":"qin","year":"2004","journal-title":"International Symposium on Quality Electronic Design"}],"event":{"name":"2015 19th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2015,6,26]]},"location":"Ahmedabad, India","end":{"date-parts":[[2015,6,29]]}},"container-title":["2015 19th International Symposium on VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7166536\/7208044\/07208097.pdf?arnumber=7208097","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T14:01:43Z","timestamp":1498226503000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7208097\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/isvdat.2015.7208097","relation":{},"subject":[],"published":{"date-parts":[[2015,6]]}}}