{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T05:04:38Z","timestamp":1775451878235,"version":"3.50.1"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,6]]},"DOI":"10.1109\/isvdat.2015.7208150","type":"proceedings-article","created":{"date-parts":[[2015,8,20]],"date-time":"2015-08-20T21:53:11Z","timestamp":1440107591000},"page":"1-6","source":"Crossref","is-referenced-by-count":11,"title":["Low power, high speed error tolerant multiplier using approximate adders"],"prefix":"10.1109","author":[{"given":"K. Manikantta","family":"Reddy","sequence":"first","affiliation":[]},{"given":"Y. B.","family":"Nithin Kumar","sequence":"additional","affiliation":[]},{"given":"Dheeraj","family":"Sharma","sequence":"additional","affiliation":[]},{"given":"M. H.","family":"Vasantha","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2006649"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.938377"},{"key":"ref12","first-page":"13","article-title":"Multiplier energy reduction through bypassing of partial products","volume":"2","author":"ni ohban","year":"2002","journal-title":"Proc IEEE Int Conf on Circuits and Systems"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/SOCCON.2009.5398054"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2217962"},{"key":"ref15","author":"rabaey","year":"2014","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.604077"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2009.5336238"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"1225","DOI":"10.1109\/TVLSI.2009.2020591","article-title":"Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing","volume":"18","author":"zhu","year":"2010","journal-title":"IEEE Trans on Very Large Scale Integration Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380853"},{"key":"ref8","first-page":"1","article-title":"High-performance low-power carry speculative addition with variable latency","author":"lin","year":"2014","journal-title":"IEEE Trans on Very Large Scale Integration Systems"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691108"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000675"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/92.974895"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810788"}],"event":{"name":"2015 19th International Symposium on VLSI Design and Test (VDAT)","location":"Ahmedabad","start":{"date-parts":[[2015,6,26]]},"end":{"date-parts":[[2015,6,29]]}},"container-title":["2015 19th International Symposium on VLSI Design and Test"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7166536\/7208044\/07208150.pdf?arnumber=7208150","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,9,3]],"date-time":"2020-09-03T23:36:32Z","timestamp":1599176192000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7208150\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/isvdat.2015.7208150","relation":{},"subject":[],"published":{"date-parts":[[2015,6]]}}}