{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,29]],"date-time":"2025-11-29T07:53:26Z","timestamp":1764402806982,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,5]]},"DOI":"10.1109\/isvdat.2016.8064863","type":"proceedings-article","created":{"date-parts":[[2017,10,12]],"date-time":"2017-10-12T16:40:08Z","timestamp":1507826408000},"page":"1-6","source":"Crossref","is-referenced-by-count":5,"title":["A method to design a comparator for sampled data processing applications"],"prefix":"10.1109","author":[{"given":"Rama Prasad","family":"Acharya","sequence":"first","affiliation":[]},{"given":"Abir J","family":"Mondal","sequence":"additional","affiliation":[]},{"given":"Alak","family":"Majumder","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19982348"},{"journal-title":"Digital Design","year":"1991","author":"mano","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.871331"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.807409"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.899856"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/el:20063083"},{"key":"ref2","first-page":"28","article-title":"A 670 ps, 64 bit dynamic low-power adder design","volume":"1","author":"woo","year":"2000","journal-title":"Circuits and Systems 2000 Proceedings ISCAS 2000 Geneva The 2000 IEEE International Symposium on"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.2008063"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"192","DOI":"10.1109\/VLSIC.2000.852887","article-title":"470 ps 64-bit parallel binary adder [for cpu chip]","author":"park","year":"2000","journal-title":"VLSI Circuits 2000 Digest of Technical Papers 2000 Symposium on"}],"event":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2016,5,24]]},"location":"Guwahati, India","end":{"date-parts":[[2016,5,27]]}},"container-title":["2016 20th International Symposium on VLSI Design and Test (VDAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8059694\/8064831\/08064863.pdf?arnumber=8064863","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,4]],"date-time":"2019-10-04T11:53:28Z","timestamp":1570190008000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8064863\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/isvdat.2016.8064863","relation":{},"subject":[],"published":{"date-parts":[[2016,5]]}}}