{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T11:03:30Z","timestamp":1725707010857},"reference-count":3,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,5]]},"DOI":"10.1109\/isvdat.2016.8064899","type":"proceedings-article","created":{"date-parts":[[2017,10,12]],"date-time":"2017-10-12T16:40:08Z","timestamp":1507826408000},"page":"1-2","source":"Crossref","is-referenced-by-count":1,"title":["Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell"],"prefix":"10.1109","author":[{"given":"Pulkit","family":"Sharma","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Anusha","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Bharath","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jasmine K.","family":"Gulati","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Preet K.","family":"Walia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sumit J.","family":"Darak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2014.7004186"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2014.6908559"},{"key":"ref1","first-page":"164","article-title":"Cmos vlsi dsign a circuitand systems perspective","author":"weste","year":"2005","journal-title":"PIE"}],"event":{"name":"2016 20th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2016,5,24]]},"location":"Guwahati, India","end":{"date-parts":[[2016,5,27]]}},"container-title":["2016 20th International Symposium on VLSI Design and Test (VDAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8059694\/8064831\/08064899.pdf?arnumber=8064899","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,11,30]],"date-time":"2017-11-30T16:04:40Z","timestamp":1512057880000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8064899\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,5]]},"references-count":3,"URL":"https:\/\/doi.org\/10.1109\/isvdat.2016.8064899","relation":{},"subject":[],"published":{"date-parts":[[2016,5]]}}}