{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T22:05:55Z","timestamp":1725401155733},"reference-count":14,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isvlsi.2004.1339527","type":"proceedings-article","created":{"date-parts":[[2004,10,4]],"date-time":"2004-10-04T18:08:32Z","timestamp":1096913312000},"page":"179-184","source":"Crossref","is-referenced-by-count":0,"title":["Practical test architecture optimization for system-on-a-chip under floorplanning constraints"],"prefix":"10.1109","author":[{"given":"M.","family":"Sugihara","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Murakami","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Y.","family":"Matsunaga","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743146"},{"journal-title":"IEEE P1500 Standard for Embedded Core Test","year":"0","key":"14"},{"key":"11","doi-asserted-by":"crossref","first-page":"134","DOI":"10.1145\/343647.343719","article-title":"Analysis and minimization of test time in a combined BIST and external test approach","author":"sugihara","year":"2000","journal-title":"Design Automation and Test in Europe Conference"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2002.995014"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337531"},{"journal-title":"Complexity and Approximation Combinatorial Optimization Problems and Their Approximability Properties","year":"1999","author":"ausiello","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743185"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743187"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1023\/A:1014916913577"},{"journal-title":"ILOG CPLEX 8 1 Reference Manual","year":"2002","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/371254.371258"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/43.875306"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894301"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894302"}],"event":{"name":"IEEE Computer Society Annual Symposium on VLSI","acronym":"ISVLSI-04","location":"Lafayette, LA, USA"},"container-title":["IEEE Computer Society Annual Symposium on VLSI"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9292\/29536\/01339527.pdf?arnumber=1339527","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,26]],"date-time":"2021-06-26T04:54:42Z","timestamp":1624683282000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1339527\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/isvlsi.2004.1339527","relation":{},"subject":[]}}