{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,21]],"date-time":"2026-07-21T14:23:55Z","timestamp":1784643835054,"version":"3.55.0"},"reference-count":13,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isvlsi.2004.1339528","type":"proceedings-article","created":{"date-parts":[[2004,10,4]],"date-time":"2004-10-04T18:08:32Z","timestamp":1096913312000},"page":"187-192","source":"Crossref","is-referenced-by-count":19,"title":["Control and data flow graph extraction for high-level synthesis"],"prefix":"10.1109","author":[{"given":"R.","family":"Namballa","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"N.","family":"Ranganathan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"A.","family":"Ejnioui","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/5.293155"},{"key":"11","author":"sander","year":"1995","journal-title":"VCG Visualization of Compiler Graphs"},{"key":"12","article-title":"Task graph extraction for embedded system synthesis","author":"vallerio","year":"2003","journal-title":"Proc IEEE VLSI Design Conf"},{"key":"3","article-title":"A cdfg model for synthesis from vhdl","author":"amellal","year":"1997","journal-title":"Technical Report Ecole Polytechnique de Montreal"},{"key":"2","first-page":"1666","article-title":"Scheduling of a control and data flow graph","volume":"3","author":"amellal","year":"1993","journal-title":"IEEE Int Symp on Circuits and Systems"},{"key":"1","author":"aho","year":"1997","journal-title":"Compilers Principles Techniques and Tools"},{"key":"10","author":"park","year":"2002","journal-title":"VDT VHDL Developer's Toolkit"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/HSC.1998.666245"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/43.31534"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/92.748204"},{"key":"4","author":"bhaskar","year":"1999","journal-title":"A VHDL Primer"},{"key":"9","first-page":"464","article-title":"A formal approach to scheduling problem in data path synthesis","volume":"10","author":"hwang","year":"1991","journal-title":"Proc IEEE Int Conf CAD"},{"key":"8","author":"govindarajan","year":"0","journal-title":"Dependency Analysis and Operation Graph Generation for High-level Synthesis from Behavioral Vhdl"}],"event":{"name":"IEEE Computer Society Annual Symposium on VLSI","location":"Lafayette, LA, USA","acronym":"ISVLSI-04"},"container-title":["IEEE Computer Society Annual Symposium on VLSI"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9292\/29536\/01339528.pdf?arnumber=1339528","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T01:22:27Z","timestamp":1489454547000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1339528\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/isvlsi.2004.1339528","relation":{},"subject":[]}}