{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T12:09:12Z","timestamp":1767182952559},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/isvlsi.2005.53","type":"proceedings-article","created":{"date-parts":[[2005,5,24]],"date-time":"2005-05-24T10:52:03Z","timestamp":1116931923000},"page":"156-161","source":"Crossref","is-referenced-by-count":45,"title":["On Reducing Peak Current and Power during Test"],"prefix":"10.1109","author":[{"family":"Wei Li","sequence":"first","affiliation":[]},{"given":"S.M.","family":"Reddy","sequence":"additional","affiliation":[]},{"given":"I.","family":"Pomeranz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"\"Plinciples of CMOS VLSI Design A System Perspective\" 2nd Ed","year":"1992","author":"eshraghian","key":"13"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386971"},{"key":"11","first-page":"26","article-title":"Test power reduction with multiple capture orders","author":"lee","year":"2004","journal-title":"Proc ATS"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996706"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"key":"2","first-page":"342","article-title":"Model for delay faults based upon paths","author":"smith","year":"1985","journal-title":"Proc ITC"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295104"},{"key":"10","first-page":"129","article-title":"Scan architecture for shift and capture cycle power reduction","author":"rosinger","year":"2002","journal-title":"Proc DFT"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011128"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843824"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805616"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/43.736572"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1999.810734"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012710"}],"event":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","location":"Tampa, FL, USA"},"container-title":["IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9780\/30846\/01430126.pdf?arnumber=1430126","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T13:45:34Z","timestamp":1489499134000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1430126\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/isvlsi.2005.53","relation":{},"subject":[]}}