{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:16:07Z","timestamp":1763468167598,"version":"3.28.0"},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,8]]},"DOI":"10.1109\/isvlsi.2013.6654621","type":"proceedings-article","created":{"date-parts":[[2013,11,11]],"date-time":"2013-11-11T22:23:30Z","timestamp":1384208610000},"page":"46-51","source":"Crossref","is-referenced-by-count":2,"title":["A study on polymorphing superscalar processor dynamically to improve power efficiency"],"prefix":"10.1109","author":[{"given":"Sudarshan","family":"Srinivasan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rance","family":"Rodrigues","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arunachalam","family":"Annamalai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Israel","family":"Koren","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sandip","family":"Kundu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"crossref","first-page":"927","DOI":"10.1145\/1629911.1630149","article-title":"efficient program scheduling for heterogeneous multi-core processors","author":"jian chen","year":"2009","journal-title":"2009 46th ACM\/IEEE Design Automation Conference dac"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785573"},{"key":"18","doi-asserted-by":"crossref","DOI":"10.1145\/1531793.1531804","article-title":"Hass: A scheduler for heterogeneous multicore systems","volume":"43","author":"shelepov","year":"2009","journal-title":"SIGOPS Oper Syst Rev"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086698"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.36"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.41"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391666"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1755913.1755928"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.37"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854283"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/859654.859657"},{"key":"22","doi-asserted-by":"crossref","first-page":"213","DOI":"10.1145\/2366231.2337184","article-title":"Scheduling heterogeneous multi-cores through performance impact estimation (pie)","author":"craeynest","year":"2012","journal-title":"Proceedings of the 39th Annual International Symposium on Computer Architecture Ser ISCA '12"},{"key":"23","doi-asserted-by":"crossref","first-page":"62","DOI":"10.1145\/1945023.1945032","article-title":"Efficient interaction between OS and architecture in heterogeneous platforms","volume":"45","author":"srinivasan","year":"2011","journal-title":"SIGOPS Oper Syst Rev"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.12"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.18"},{"journal-title":"The Microarchitecture of Intel AMD and VIA CPU","year":"0","author":"fog","key":"26"},{"journal-title":"SESC SuperESCalar Simulator","year":"2005","author":"renau","key":"27"},{"journal-title":"CACTI 3 0 An integrated cache timing power and area model","year":"2001","author":"shivakumar","key":"28"},{"key":"29","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253185"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2008.209"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1128022.1128029"},{"journal-title":"White Paper from A Few Cores to Many A Tera-scale Computing Research Review","year":"2006","author":"held","key":"1"},{"journal-title":"The Standard Performance Evaluation Corporation (Spec CPI2000 Suite)","year":"0","key":"30"},{"key":"7","first-page":"59","article-title":"Scalable thread scheduling in asymmetric multicores for power efficiency","year":"0","journal-title":"Computer Architecture and High Performance Computing (SBAC-PAD) 2012 IEEE 24th International Symposium On 2012"},{"key":"6","doi-asserted-by":"crossref","DOI":"10.1145\/2390191.2390196","article-title":"Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing","volume":"18","author":"rodrigues","year":"2013","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1508284.1508274"},{"key":"31","article-title":"Mediabench: A tool for evaluating and synthesizing multimedia and communicatons systems","author":"lee","year":"0","journal-title":"Proceedings of the 30th Annual ACM\/IEEE International Symposium on Microarchitecture Ser MICRO 30 1997"},{"journal-title":"Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques Ser PACT '06 2006","article-title":"Core architecture optimization for heterogeneous chip multiprocessors","year":"0","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2004.1347928"},{"journal-title":"Big little Processing with Arm cortex-a15 and cortexa7","year":"2011","author":"greenhalgh","key":"8"}],"event":{"name":"2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","start":{"date-parts":[[2013,8,5]]},"location":"Natal, Brazil","end":{"date-parts":[[2013,8,7]]}},"container-title":["2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6646390\/6654605\/06654621.pdf?arnumber=6654621","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,7]],"date-time":"2020-08-07T18:52:02Z","timestamp":1596826322000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6654621\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,8]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/isvlsi.2013.6654621","relation":{},"subject":[],"published":{"date-parts":[[2013,8]]}}}