{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,22]],"date-time":"2026-01-22T00:42:33Z","timestamp":1769042553119,"version":"3.49.0"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,6,20]],"date-time":"2023-06-20T00:00:00Z","timestamp":1687219200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,6,20]],"date-time":"2023-06-20T00:00:00Z","timestamp":1687219200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,6,20]]},"DOI":"10.1109\/isvlsi59464.2023.10238626","type":"proceedings-article","created":{"date-parts":[[2023,9,6]],"date-time":"2023-09-06T17:23:19Z","timestamp":1694020999000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs"],"prefix":"10.1109","author":[{"given":"Grant","family":"Brown","sequence":"first","affiliation":[{"name":"University of Utah"}]},{"given":"Ganesh","family":"Gore","sequence":"additional","affiliation":[{"name":"University of Utah"}]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[{"name":"University of Utah"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2191554"},{"key":"ref12","first-page":"56","article-title":"Design flow for embedded FPGAs based on a flexible architecture template","author":"neumann","year":"2008","journal-title":"DATE"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112223"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00065"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2018.00026"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1960397.1960407"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2300174"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mcm.2009.08.024"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2015.7085442"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2008.14"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653738"},{"key":"ref9","first-page":"484","article-title":"An O (bn\/sup 2\/) time algorithm for optimal buffer insertion with b buffer types","volume":"25","author":"li","year":"0","journal-title":"IEEE Trans CAD of IC"},{"key":"ref4","article-title":"A Scalable and Robust Hierarchical Floor-planning to Enable 24-hour Prototyping for 100k-LUT FPGAs","author":"gore","year":"2021","journal-title":"ISPD"},{"key":"ref3","first-page":"799","article-title":"Zero skew clock routing with minimum wirelength","volume":"39","author":"chao","year":"1992","journal-title":"IEEE TC&S II Analog and DSP"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1155\/2011\/407507"},{"key":"ref5","first-page":"1","article-title":"Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow","author":"kim","year":"2015","journal-title":"FPL"}],"event":{"name":"2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","location":"Foz do Iguacu, Brazil","start":{"date-parts":[[2023,6,20]]},"end":{"date-parts":[[2023,6,23]]}},"container-title":["2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10238464\/10238482\/10238626.pdf?arnumber=10238626","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T18:01:57Z","timestamp":1695664917000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10238626\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,20]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/isvlsi59464.2023.10238626","relation":{},"subject":[],"published":{"date-parts":[[2023,6,20]]}}}