{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T01:43:10Z","timestamp":1740102190475,"version":"3.37.3"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,6,20]],"date-time":"2023-06-20T00:00:00Z","timestamp":1687219200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,6,20]],"date-time":"2023-06-20T00:00:00Z","timestamp":1687219200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002322","name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002322","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003593","name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003593","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004263","name":"Funda\u00e7\u00e3o de Amparo \u00e0 Pesquisa do Estado do Rio Grande do Sul","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004263","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,6,20]]},"DOI":"10.1109\/isvlsi59464.2023.10238642","type":"proceedings-article","created":{"date-parts":[[2023,9,6]],"date-time":"2023-09-06T17:23:19Z","timestamp":1694020999000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis"],"prefix":"10.1109","author":[{"given":"Gabriel","family":"Ammes","sequence":"first","affiliation":[{"name":"Federal University of Rio Grande do Sul (UFRGS),PPGC,Porto Alegre,Brazil"}]},{"given":"Paulo F.","family":"Butzen","sequence":"additional","affiliation":[{"name":"Federal University of Rio Grande do Sul (UFRGS),PGMICRO,Porto Alegre,Brazil"}]},{"given":"Andr\u00e9 I.","family":"Reis","sequence":"additional","affiliation":[{"name":"Federal University of Rio Grande do Sul (UFRGS),PPGC,Porto Alegre,Brazil"}]},{"given":"Renato P.","family":"Ribas","sequence":"additional","affiliation":[{"name":"Federal University of Rio Grande do Sul (UFRGS),PGMICRO,Porto Alegre,Brazil"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116296"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3143489"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9473952"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218627"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2890532"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240795"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2893356"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2505723"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774604"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3394885.3431550"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586132"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DCAS53974.2022.9845591"},{"journal-title":"ABC A System for Sequential Synthesis and Verification","year":"0","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2958605"},{"journal-title":"IWLS'93 Benchmark Set Version 4 0","year":"1993","author":"mcelvain","key":"ref25"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147048"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4613-2821-6"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2017.7968435"},{"key":"ref7","article-title":"Synthesis and Optimization of Digital Circuits","author":"micheli","year":"1994","journal-title":"McGraw-Hill Higher Education"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456913"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2019.10.001"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7926993"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.29292\/jics.v17i3.661"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.3014430"}],"event":{"name":"2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","start":{"date-parts":[[2023,6,20]]},"location":"Foz do Iguacu, Brazil","end":{"date-parts":[[2023,6,23]]}},"container-title":["2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10238464\/10238482\/10238642.pdf?arnumber=10238642","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,25]],"date-time":"2023-09-25T18:01:59Z","timestamp":1695664919000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10238642\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,20]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/isvlsi59464.2023.10238642","relation":{},"subject":[],"published":{"date-parts":[[2023,6,20]]}}}