{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T05:10:21Z","timestamp":1756357821532,"version":"3.44.0"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,7,6]],"date-time":"2025-07-06T00:00:00Z","timestamp":1751760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,6]],"date-time":"2025-07-06T00:00:00Z","timestamp":1751760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,7,6]]},"DOI":"10.1109\/isvlsi65124.2025.11130256","type":"proceedings-article","created":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T18:20:15Z","timestamp":1756318815000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing Optimization"],"prefix":"10.1109","author":[{"given":"Yiyu","family":"Wang","sequence":"first","affiliation":[{"name":"Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China,100191"}]},{"given":"Vasilis F.","family":"Pavlidis","sequence":"additional","affiliation":[{"name":"Aristotle University of Thessaloniki,ECE Department,Thessaloniki,Greece"}]},{"given":"Rui","family":"Wang","sequence":"additional","affiliation":[{"name":"Beihang University,School of Computer Science and Engineering,Beijing,China,100191"}]},{"given":"Yuanqing","family":"Cheng","sequence":"additional","affiliation":[{"name":"Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China,100191"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2024.112189"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC53496.2022.9772831"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1811100.1811107"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/s11081-016-9317-2"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2010.2099590"},{"article-title":"Graph Algorithms for VLSI Power and Clock Networks","year":"2022","author":"Bairamkulov","key":"ref6"},{"key":"ref7","first-page":"1","article-title":"An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem","volume-title":"Proceedings of the 50th annual design automation conference","author":"Kim"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2451916.2451956"},{"issue":"1","key":"ref9","first-page":"103","article-title":"Introduction to vlsi systems: A logic, circuit, and system perspective\u201d by ming-bo lin","volume":"2","author":"Liam","year":"2023","journal-title":"Cosmic Journal of Physics"},{"volume-title":"IBM","key":"ref10"}],"event":{"name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","start":{"date-parts":[[2025,7,6]]},"location":"Kalamata, Greece","end":{"date-parts":[[2025,7,9]]}},"container-title":["2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11129697\/11130193\/11130256.pdf?arnumber=11130256","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T04:31:46Z","timestamp":1756355506000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11130256\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,6]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/isvlsi65124.2025.11130256","relation":{},"subject":[],"published":{"date-parts":[[2025,7,6]]}}}