{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T05:10:19Z","timestamp":1756357819617,"version":"3.44.0"},"reference-count":8,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,7,6]],"date-time":"2025-07-06T00:00:00Z","timestamp":1751760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,6]],"date-time":"2025-07-06T00:00:00Z","timestamp":1751760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,7,6]]},"DOI":"10.1109\/isvlsi65124.2025.11130278","type":"proceedings-article","created":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T18:20:15Z","timestamp":1756318815000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["Accelerating Equation Solvers using Gauss-Jacobi on Multi-FPGA Systems with Ring NoC"],"prefix":"10.1109","author":[{"given":"Shruti","family":"Patkar","sequence":"first","affiliation":[{"name":"IIT,Department of Electrical and Electronics Engineering,Guwahati"}]},{"family":"Harsh","sequence":"additional","affiliation":[{"name":"IIT,Department of Electrical Engineering,Bombay"}]},{"given":"Souraja","family":"Kundu","sequence":"additional","affiliation":[{"name":"IIT,Department of Electrical and Electronics Engineering,Guwahati"}]},{"given":"Gaurav","family":"Trivedi","sequence":"additional","affiliation":[{"name":"IIT,Department of Electrical and Electronics Engineering,Guwahati"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/NORCHP.2004.1423811"},{"volume-title":"A ring router microarchitecture for nocs","year":"2020","author":"Wu","key":"ref2"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/DATE.2011.5763134"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.5120\/ijca2016911313"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/FPL50879.2020.00068"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/FPL.2012.6339276"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1088\/1742-6596\/2438\/1\/012023"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/ASAP57973.2023.00025"}],"event":{"name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","start":{"date-parts":[[2025,7,6]]},"location":"Kalamata, Greece","end":{"date-parts":[[2025,7,9]]}},"container-title":["2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11129697\/11130193\/11130278.pdf?arnumber=11130278","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T04:32:09Z","timestamp":1756355529000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11130278\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,6]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/isvlsi65124.2025.11130278","relation":{},"subject":[],"published":{"date-parts":[[2025,7,6]]}}}