{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T05:10:18Z","timestamp":1756357818422,"version":"3.44.0"},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,7,6]],"date-time":"2025-07-06T00:00:00Z","timestamp":1751760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,6]],"date-time":"2025-07-06T00:00:00Z","timestamp":1751760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,7,6]]},"DOI":"10.1109\/isvlsi65124.2025.11130285","type":"proceedings-article","created":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T18:20:15Z","timestamp":1756318815000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGA"],"prefix":"10.1109","author":[{"given":"Ardhendu","family":"Sarkar","sequence":"first","affiliation":[{"name":"Indian Institute of Engineering Science & Technology,Dept. of Computer Science & Technology,Shibpur,Howrah,India"}]},{"given":"Sriparna","family":"Mandal","sequence":"additional","affiliation":[{"name":"Indian Institute of Engineering Science & Technology,Dept. of Computer Science & Technology,Shibpur,Howrah,India"}]},{"given":"Surajeet","family":"Ghosh","sequence":"additional","affiliation":[{"name":"Indian Institute of Engineering Science & Technology,Dept. of Computer Science & Technology,Shibpur,Howrah,India"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1468075.1468121"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.3390\/electronics11071029"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.34"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00038"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2018.00022"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC.2019.00043"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2018.00023"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.2020PAP0017"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2022.3146509"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228588"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2854150"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s00778-011-0232-z"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689068"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2672966"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.27"}],"event":{"name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","start":{"date-parts":[[2025,7,6]]},"location":"Kalamata, Greece","end":{"date-parts":[[2025,7,9]]}},"container-title":["2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11129697\/11130193\/11130285.pdf?arnumber=11130285","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T04:32:17Z","timestamp":1756355537000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11130285\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,6]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/isvlsi65124.2025.11130285","relation":{},"subject":[],"published":{"date-parts":[[2025,7,6]]}}}