{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T05:10:21Z","timestamp":1756357821553,"version":"3.44.0"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,7,6]],"date-time":"2025-07-06T00:00:00Z","timestamp":1751760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,6]],"date-time":"2025-07-06T00:00:00Z","timestamp":1751760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,7,6]]},"DOI":"10.1109\/isvlsi65124.2025.11130306","type":"proceedings-article","created":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T18:20:15Z","timestamp":1756318815000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Boosting Scan Chain Security in a White-box through Restricted Pattern Filtering"],"prefix":"10.1109","author":[{"given":"Leon","family":"Li","sequence":"first","affiliation":[{"name":"University of California La Jolla,San Diego,California,U.S.A"}]},{"given":"Alex","family":"Orailoglu","sequence":"additional","affiliation":[{"name":"University of California La Jolla,San Diego,California,U.S.A"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386969"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2005.193787"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1929943.1929952"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2505014"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-89754-5_18"},{"key":"ref7","article-title":"Encrypt flipflop: A novel logic encryption technique for sequential circuits","author":"Karmakar","year":"2018","journal-title":"arXiv preprint arXiv:1801.04961"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2017.7928947"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194596"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287693"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116197"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2925237"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3080257"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-03515-4_6"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-13039-2_11"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2818722"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ETS61313.2024.10567195"},{"key":"ref18","first-page":"9","article-title":"Design principles for tamperresistant smartcard processors","volume":"99","author":"K\u00c3\u00b6mmerling","year":"1999","journal-title":"Smartcard"},{"key":"ref19","first-page":"161","article-title":"La cryptographie militaire","author":"Kerckhoffs","year":"1883","journal-title":"Journal des Sciences Militaires"},{"key":"ref20","first-page":"93","article-title":"Atalanta: An efficient ATPG for combinational circuits","volume-title":"Technical Report","author":"Lee"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2005.36"},{"key":"ref22","first-page":"26","article-title":"Security on IoT devices with secure elements","volume-title":"Embedded World Conference","author":"Schl\u00c3\u00a4pfer"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2018.04.007"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ITC51657.2024.00028"}],"event":{"name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","start":{"date-parts":[[2025,7,6]]},"location":"Kalamata, Greece","end":{"date-parts":[[2025,7,9]]}},"container-title":["2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11129697\/11130193\/11130306.pdf?arnumber=11130306","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T04:32:37Z","timestamp":1756355557000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11130306\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,6]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/isvlsi65124.2025.11130306","relation":{},"subject":[],"published":{"date-parts":[[2025,7,6]]}}}