{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T05:10:23Z","timestamp":1756357823315,"version":"3.44.0"},"reference-count":17,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,7,6]],"date-time":"2025-07-06T00:00:00Z","timestamp":1751760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,6]],"date-time":"2025-07-06T00:00:00Z","timestamp":1751760000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100007309","name":"Applied Materials","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007309","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100006470","name":"Aristotle University of Thessaloniki","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100006470","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100000780","name":"European Commission","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000780","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,7,6]]},"DOI":"10.1109\/isvlsi65124.2025.11130311","type":"proceedings-article","created":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T18:20:15Z","timestamp":1756318815000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Enhancing Performance of Floating Point Units Using Parallel Prefix Adders"],"prefix":"10.1109","author":[{"given":"Andreas-Efstathios","family":"Eleftheriadis","sequence":"first","affiliation":[{"name":"Aristotle University of Thessaloniki,Department of Electrical and Computer Engineering"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thomas","family":"Noulis","sequence":"additional","affiliation":[{"name":"Aristotle University of Thessaloniki,Department of Physics"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georgios","family":"Keramidas","sequence":"additional","affiliation":[{"name":"Aristotle University of Thessaloniki,School of Informatics"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vasilis F.","family":"Pavlidis","sequence":"additional","affiliation":[{"name":"Aristotle University of Thessaloniki,Department of Electrical and Computer Engineering"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1973.5009159"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/322217.322232"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675982"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1987.6158699"},{"key":"ref5","first-page":"1","article-title":"Comparative Study of Parallel Prefix Adders Based on Carry Propagation and Sum Propagation","volume-title":"International Conference on Power, Instrumentation, Control and Computing","author":"Anagha"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SPICES52834.2022.9774131"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICICCT.2018.8473087"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICECA.2019.8821925"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SCES50439.2020.9236737"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCMC.2019.8819779"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2021.3068729"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/WiSPNET.2017.8300155"},{"key":"ref13","first-page":"1063","article-title":"Design and Analysis of KoggeStone and Han-Carlson Adders in 130 nm CMOS Technology","volume":"05","author":"Ramasamy","year":"2018","journal-title":"International Journal of Research"},{"key":"ref14","first-page":"1448","article-title":"Design and Comparative Analysis of Various Adders through Pipelining Techniques","volume":"07","author":"Aakansha","year":"2016","journal-title":"International Journal of Computer Science and Information Technologies"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1958.5222579"},{"article-title":"SystemVerilog-ParallelPrefixAdders","year":"2024","author":"Eleftheriadis","key":"ref16"},{"author":"Systems","key":"ref17","article-title":"Genus Synthesis Solution Datasheet"}],"event":{"name":"2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","start":{"date-parts":[[2025,7,6]]},"location":"Kalamata, Greece","end":{"date-parts":[[2025,7,9]]}},"container-title":["2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11129697\/11130193\/11130311.pdf?arnumber=11130311","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T04:32:45Z","timestamp":1756355565000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11130311\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,6]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/isvlsi65124.2025.11130311","relation":{},"subject":[],"published":{"date-parts":[[2025,7,6]]}}}