{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,3]],"date-time":"2026-04-03T06:59:15Z","timestamp":1775199555137,"version":"3.50.1"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,9,12]],"date-time":"2023-09-12T00:00:00Z","timestamp":1694476800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,9,12]],"date-time":"2023-09-12T00:00:00Z","timestamp":1694476800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,9,12]]},"DOI":"10.1109\/itc-asia58802.2023.10301173","type":"proceedings-article","created":{"date-parts":[[2023,11,1]],"date-time":"2023-11-01T18:07:23Z","timestamp":1698862043000},"page":"1-6","source":"Crossref","is-referenced-by-count":5,"title":["Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs"],"prefix":"10.1109","author":[{"given":"Meng-Shan","family":"Wu","sequence":"first","affiliation":[{"name":"National Central University,Department of Electrical Engineering,Taoyuan,Taiwan,320"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yen-Lin","family":"Chua","sequence":"additional","affiliation":[{"name":"National Central University,Department of Electrical Engineering,Taoyuan,Taiwan,320"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin-Fu","family":"Li","sequence":"additional","affiliation":[{"name":"National Central University,Department of Electrical Engineering,Taoyuan,Taiwan,320"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yun-Ting","family":"Chuan","sequence":"additional","affiliation":[{"name":"Chung Yuan Christian University,Department of Electronic Engineering,Taoyuan,Taiwan,320"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shih-Hsu","family":"Huang","sequence":"additional","affiliation":[{"name":"Chung Yuan Christian University,Department of Electronic Engineering,Taoyuan,Taiwan,320"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.3040425"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2913207"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/24.52622"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2015.7338359"},{"key":"ref14","article-title":"MBIST-supported trim adjustment to compensate thermal behavior of MRAM","author":"munch","year":"2022","journal-title":"Proc IEEE European Test Symp (ETS)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062955"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2779151"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662444"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2934685"},{"key":"ref21","article-title":"MBIST-supported trim-search test time reduction for STT-MRAM","author":"munch","year":"2022","journal-title":"Proc IEEE VLSI Test Symp (VTS)"},{"key":"ref2","first-page":"135","article-title":"A 3.3ns-access-time 71.2?W\/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture","author":"noguchi","year":"2015","journal-title":"Proc IEEE Int’l Solid-State Cir Conf (ISSCC)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2016.2521712"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2889106"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351201"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ITC44778.2020.9325218"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ETS48528.2020.9131564"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2014.2374291"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2606438"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2016.28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2327337"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2544860"},{"key":"ref6","first-page":"1109","article-title":"A double-sensing-margin offset-canceling dual-stage sening circuit for resistive nonvolatile memory","volume":"62","author":"na","year":"2015","journal-title":"IEEE Trans on Circuits and Systems II Analog and Digital Signal Processing"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2294095"}],"event":{"name":"2023 IEEE International Test Conference in Asia (ITC-Asia)","location":"Matsue, Japan","start":{"date-parts":[[2023,9,12]]},"end":{"date-parts":[[2023,9,14]]}},"container-title":["2023 IEEE International Test Conference in Asia (ITC-Asia)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10301149\/10301156\/10301173.pdf?arnumber=10301173","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,11,27]],"date-time":"2023-11-27T19:32:40Z","timestamp":1701113560000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10301173\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,12]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/itc-asia58802.2023.10301173","relation":{},"subject":[],"published":{"date-parts":[[2023,9,12]]}}}