{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T07:33:36Z","timestamp":1725608016063},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,11,1]]},"DOI":"10.1109\/itc44778.2020.9325244","type":"proceedings-article","created":{"date-parts":[[2021,1,20]],"date-time":"2021-01-20T21:17:10Z","timestamp":1611177430000},"page":"1-10","source":"Crossref","is-referenced-by-count":1,"title":["High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips"],"prefix":"10.1109","author":[{"given":"Zeye","family":"Liu","sequence":"first","affiliation":[]},{"given":"R. D.","family":"Shawn Blanton","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2017.7968231"},{"journal-title":"A logic test chip for optimal test and diagnosis","year":"2018","author":"niewenhuis","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1997.628897"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805857"},{"journal-title":"OpenSPARC T2 processor","year":"0","key":"ref14"},{"key":"ref15","first-page":"1","article-title":"A Diagnostic Test Generation System","author":"zhang","year":"2000","journal-title":"IEEE International Test Conference"},{"journal-title":"Python Reference Manual","year":"1995","author":"rossum","key":"ref16"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035345"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.2006.1638792"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00074"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2015.7342379"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2017.8242041"},{"key":"ref7","first-page":"109","article-title":"Achieving 100% Cell-aware Coverage by Design","author":"liu","year":"2016","journal-title":"Proc Design Automation and Test in Europe"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-12-234106-9.50014-3"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2004.835724(410) 17"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ITC44170.2019.9000131"}],"event":{"name":"2020 IEEE International Test Conference (ITC)","start":{"date-parts":[[2020,11,1]]},"location":"Washington, DC, USA","end":{"date-parts":[[2020,11,6]]}},"container-title":["2020 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9325188\/9325208\/09325244.pdf?arnumber=9325244","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T21:51:21Z","timestamp":1656453081000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9325244\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,1]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/itc44778.2020.9325244","relation":{},"subject":[],"published":{"date-parts":[[2020,11,1]]}}}