{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T01:47:53Z","timestamp":1725587273909},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,11,1]],"date-time":"2020-11-01T00:00:00Z","timestamp":1604188800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,11,1]]},"DOI":"10.1109\/itc44778.2020.9325265","type":"proceedings-article","created":{"date-parts":[[2021,1,20]],"date-time":"2021-01-20T21:17:10Z","timestamp":1611177430000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["Test Challenges of Intel IA Cores"],"prefix":"10.1109","author":[{"given":"Uri","family":"Shpiro","sequence":"first","affiliation":[]},{"given":"Khen","family":"Wee","sequence":"additional","affiliation":[]},{"given":"Kun-Han","family":"Tsai","sequence":"additional","affiliation":[]},{"given":"Justyna","family":"Zawada","sequence":"additional","affiliation":[]},{"given":"Xijiang","family":"Lin","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"462","article-title":"A logic design structure for LSI testability","author":"eichelberger","year":"1977","journal-title":"Design Automation Conference"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041808"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910963"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2009.46"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-0928-2_9"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783730"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2017.41"},{"key":"ref5","first-page":"688","article-title":"Test Generation in the Presence of Timing Exceptions and Constraints","author":"goswami","year":"2007","journal-title":"Design Automation Conference"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2008.45"},{"key":"ref7","first-page":"1","article-title":"The challenge of testing the ARM Cortex-A8TM microprocessor core","author":"mclaurin","year":"2006","journal-title":"International Test Conference"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606671"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651930"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS47505.2019.000-6"}],"event":{"name":"2020 IEEE International Test Conference (ITC)","start":{"date-parts":[[2020,11,1]]},"location":"Washington, DC, USA","end":{"date-parts":[[2020,11,6]]}},"container-title":["2020 IEEE International Test Conference (ITC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9325188\/9325208\/09325265.pdf?arnumber=9325265","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T21:58:11Z","timestamp":1656453491000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9325265\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,1]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/itc44778.2020.9325265","relation":{},"subject":[],"published":{"date-parts":[[2020,11,1]]}}}