{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,6]],"date-time":"2026-10-06T05:10:56Z","timestamp":1791263456702,"version":"4.1.0"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1109\/itcc.2004.1286716","type":"proceedings-article","created":{"date-parts":[[2004,6,10]],"date-time":"2004-06-10T14:19:45Z","timestamp":1086877185000},"page":"583-587 Vol.2","source":"Crossref","is-referenced-by-count":91,"title":["Compact and efficient encryption\/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications"],"prefix":"10.1109","author":[{"given":"G.","family":"Rouvroy","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"F.-X.","family":"Standaert","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"J.-J.","family":"Quisquater","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"J.-D.","family":"Legat","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"3","article-title":"The block cipher RIJNDAEL","author":"daemon","year":"0","journal-title":"NIST's AES Home Page"},{"key":"2","volume":"46","year":"1977","journal-title":"FIPS PUB"},{"key":"1","year":"0","journal-title":"The Spartan-3 and Virtex-II Field Programmable Gate Arrays Data Sheets"},{"key":"7","doi-asserted-by":"crossref","first-page":"334","DOI":"10.1007\/978-3-540-45238-6_27","article-title":"Efficient implementation of rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs","volume":"2779","author":"standaert","year":"0","journal-title":"Lecture Notes in Computer Science"},{"key":"6","first-page":"216","article-title":"A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES rijndael","author":"standaert","year":"0","journal-title":"Proc FPGA 2003"},{"key":"5","doi-asserted-by":"crossref","first-page":"181","DOI":"10.1007\/978-3-540-45234-8_19","article-title":"Design strategies and modified descriptions to optimize cipher FPGA implementations: Fast and compact results for DES and tripleDES","volume":"2778","author":"rouvroy","year":"0","journal-title":"Lecture Notes in Computer Science"},{"key":"4","author":"baretto","year":"0","journal-title":"The KHAZAD Legacy-level Block Cipher"},{"key":"8","first-page":"319","article-title":"Very compact FPGA implementation of the AES algorithm","volume":"2779","author":"gaj","year":"0","journal-title":"Lecture Notes in Computer Science"}],"event":{"name":"International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004.","location":"Las Vegas, NV, USA","start":{"date-parts":[[2004,4,5]]},"end":{"date-parts":[[2004,4,7]]}},"container-title":["International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9035\/28683\/01286716.pdf?arnumber=1286716","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T07:56:44Z","timestamp":1497599804000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1286716\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/itcc.2004.1286716","relation":{},"subject":[],"published":{"date-parts":[[2004]]}}}