{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T14:25:59Z","timestamp":1774448759362,"version":"3.50.1"},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,7]]},"DOI":"10.1109\/ivsw.2019.8854391","type":"proceedings-article","created":{"date-parts":[[2019,10,3]],"date-time":"2019-10-03T21:07:27Z","timestamp":1570136847000},"page":"7-12","source":"Crossref","is-referenced-by-count":26,"title":["On a Low Cost Fault Injection Framework for Security Assessment of Cyber-Physical Systems: Clock Glitch Attacks"],"prefix":"10.1109","author":[{"given":"Zahra","family":"Kazemi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Athanasios","family":"Papadimitriou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ioanna","family":"Souvatzoglou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ehsan","family":"Aerabi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mosabbah Mushir","family":"Ahmed","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Hely","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vincent","family":"Beroulle","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","author":"flynn","year":"2015","journal-title":"Chipwhisperer"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-12510-2_13"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2011.9"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.23919\/AE.2017.8053601"},{"key":"ref14","first-page":"265","author":"endo","year":"2011","journal-title":"An on-chip glitchy-clock generator for testing fault injection attacks"},{"key":"ref15","first-page":"97","article-title":"Improving fault attacks on embedded software using RISC pipeline characterization","author":"yuce","year":"2016","journal-title":"Proc &#x2013; 2015 Work Fault Diagnosis Toler Cryptogr FDTC 2015"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2014.11"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2009.34"},{"key":"ref18","first-page":"2","author":"korczyc","year":"2012","journal-title":"Evaluation of Susceptibility of FPGA-based Circuits to Fault Injection Attacks Based on Clock Glitching"},{"key":"ref19","first-page":"23","volume":"1","author":"qiao","year":"2017","journal-title":"Clock Glitch Fault Injection Attacks on an FPGA AES Implementation"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2820611"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.2147\/MDER.S50048"},{"key":"ref6","first-page":"15","author":"piscitelli","year":"2015","journal-title":"Fault attacks injection techniques and tools for simulation"},{"key":"ref5","first-page":"1","volume":"60","author":"liao","year":"2017","journal-title":"Improving DFA attacks on AES with unknown and random faults"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/GCCE.2016.7800490"},{"key":"ref7","year":"0","journal-title":"Riscure Spider"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IVSW.2018.8494843"},{"key":"ref1","first-page":"294","article-title":"A survey on IoT applications, security challenges and counter measures","author":"pawar","year":"2017","journal-title":"Int Conf Comput Anal Secur Trends CAST 2016"},{"key":"ref9","first-page":"36","article-title":"Side-Channel Attack Standard Evaluation Board SASEBO-W Specification Ver 1.1","author":"katashita","year":"2011","journal-title":"NIA 2011"}],"event":{"name":"2019 IEEE 4th International Verification and Security Workshop (IVSW)","location":"Rhodes Island, Greece","start":{"date-parts":[[2019,7,1]]},"end":{"date-parts":[[2019,7,3]]}},"container-title":["2019 IEEE 4th International Verification and Security Workshop (IVSW)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8850848\/8854381\/08854391.pdf?arnumber=8854391","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,14]],"date-time":"2022-07-14T23:16:27Z","timestamp":1657840587000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8854391\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/ivsw.2019.8854391","relation":{},"subject":[],"published":{"date-parts":[[2019,7]]}}}