{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:12:08Z","timestamp":1763467928938},"reference-count":36,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,5]]},"DOI":"10.1109\/iwmse.2009.5071386","type":"proceedings-article","created":{"date-parts":[[2009,6,16]],"date-time":"2009-06-16T17:08:52Z","timestamp":1245172132000},"page":"73-80","source":"Crossref","is-referenced-by-count":11,"title":["Phase-guided thread-to-core assignment for improved utilization of performance-asymmetric multi-core processors"],"prefix":"10.1109","author":[{"given":"Tyler","family":"Sondag","sequence":"first","affiliation":[]},{"given":"Hridesh","family":"Rajan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"0","key":"19"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1145\/1362622.1362694"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.47"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2006.11.004"},{"key":"18","article-title":"experiences and lessons learned with a portable interface to hardware performance counters","author":"dongarra","year":"2003","journal-title":"PADTAD"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1145\/1376789.1376799"},{"journal-title":"Efficient Adaptation of Multiple Microprocessor Resources for Energy Reduction Using Dynamic Optimization","year":"2005","author":"hu","key":"15"},{"year":"0","key":"34"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/871656.859637"},{"article-title":"preparing for the second stage of multi-core hardware: asymmetric (heterogeneous) cores","year":"2008","author":"gillespie","key":"13"},{"key":"14","article-title":"phase capture and prediction with applications","author":"hock","year":"2005","journal-title":"Technical Report - Com Sci Dept - University of Wisconsin-Madison"},{"year":"0","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.160"},{"journal-title":"ISCA","year":"1999","author":"merten","key":"21"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.39"},{"year":"0","key":"22"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2007.4336208"},{"article-title":"using program phases as meta-data for runtime energy optimization","year":"2004","author":"pereira","key":"24"},{"key":"25","doi-asserted-by":"crossref","DOI":"10.1145\/360128.360153","article-title":"memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures","author":"balasubramonian","year":"2000","journal-title":"Micro"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310764"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.379"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152162"},{"key":"29","article-title":"platform 2015: intel processor and platform evolution for the next decade","author":"borkar","year":"2005","journal-title":"Technical Report White Paper"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.36"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/800028.808479"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2003.1238018"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/1028976.1028999"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024414"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1272996.1273004"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/511399.511366"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1128022.1128029"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2001.953283"},{"year":"0","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253197"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003581"}],"event":{"name":"2009 ICSE Workshop on Multicore Software Engineering (IWMSE)","start":{"date-parts":[[2009,5,18]]},"location":"Vancouver, BC, Canada","end":{"date-parts":[[2009,5,18]]}},"container-title":["2009 ICSE Workshop on Multicore Software Engineering"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5061470\/5071362\/05071386.pdf?arnumber=5071386","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,14]],"date-time":"2024-03-14T17:09:05Z","timestamp":1710436145000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5071386\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,5]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/iwmse.2009.5071386","relation":{},"subject":[],"published":{"date-parts":[[2009,5]]}}}