{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T10:46:21Z","timestamp":1742381181464,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iwrsp.2003.1207043","type":"proceedings-article","created":{"date-parts":[[2004,1,23]],"date-time":"2004-01-23T23:33:03Z","timestamp":1074900783000},"page":"156-163","source":"Crossref","is-referenced-by-count":5,"title":["An instruction throughput model of superscalar processors"],"prefix":"10.1109","author":[{"given":"T.M.","family":"Taha","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.S.","family":"Wills","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Theoretical modeling of superscalar processor performance","author":"noonburg","year":"1994","journal-title":"International Symposium on Microarchitecture"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1997.569691"},{"key":"ref12","first-page":"927","article-title":"System performance analyses of out-of-order superscalar processors using analytical method","volume":"e82a","author":"kim","year":"1999","journal-title":"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPC.2000.846511"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.1999.807388"},{"article-title":"A Parallelism, Instruction Throughput, and Cycle Time Model of Computer Architectures","year":"2002","author":"taha","key":"ref15"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/2.612249"},{"key":"ref3","article-title":"A Design Space Evaluation of Grid Processor Architectures","author":"sankaralingam","year":"2001","journal-title":"International Symposium on Microarchitecture"},{"key":"ref6","first-page":"14","volume":"18","author":"normoyle","year":"1998","journal-title":"UltraSPARC-IIi expanding the boundaries of a system on a chip IEEE Micro"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"ref8","article-title":"An Illustration of the MIPS&#x00AE; R12000TM Microprocessor and OCTANE System Architecture","author":"williams","year":"1999","journal-title":"White Paper"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/2.982914"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1997.612248"},{"key":"ref1","article-title":"Intel describes billion-transistor four-core Itanium processor","author":"cataldo","year":"2002","journal-title":"EE Times"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/12.40844"}],"event":{"name":"14th IEEE International Workshop on Rapid Systems Prototyping","acronym":"IWRSP-03","location":"San Diego, CA, USA"},"container-title":["14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8579\/27166\/01207043.pdf?arnumber=1207043","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T12:56:59Z","timestamp":1489409819000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1207043\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iwrsp.2003.1207043","relation":{},"subject":[]}}