{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T18:11:54Z","timestamp":1729620714515,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iwsoc.2003.1212997","type":"proceedings-article","created":{"date-parts":[[2004,3,1]],"date-time":"2004-03-01T21:26:50Z","timestamp":1078176410000},"page":"10-15","source":"Crossref","is-referenced-by-count":4,"title":["A performance evaluation method for optimizing embedded applications"],"prefix":"10.1109","author":[{"given":"M.","family":"Grunewald","sequence":"first","affiliation":[]},{"given":"J.-C.","family":"Niemann","sequence":"additional","affiliation":[]},{"given":"U.","family":"Ruckert","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.156139"},{"key":"ref11","article-title":"An Accurate and Fine Grain Instruction-Level Energy Model Supporting Software Optimizations","author":"steinke","year":"2001","journal-title":"Proc Int Workshop on Power and Timing Modeling Optimization and Simulation (PATMOS)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379033"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(00)00053-9"},{"key":"ref4","article-title":"Implementation of a RISC Processor Core for SoC Designs-FPGA Prototype vs. ASIC Implementation","author":"langen","year":"2002","journal-title":"Proceedings of the IEEE-Workshop Heterogeneous reconfigurable Systems on Chip (SoC)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MCSA.1999.749272"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/581199.581229"},{"key":"ref5","article-title":"Power Analysis and Minimization Techniques for Embedded DSP Software","volume":"5","author":"lee","year":"1997","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"ref8","article-title":"A Dynamically Reconfigurable Hardware Accelerator for Self-Organizing Feature Maps","author":"porrmann","year":"2001","journal-title":"World Multi Conference on Systemics Cybernetics and Informatics"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1109\/ISSS.2001.957927","article-title":"Current Consumption Dynamics at Instruction and Program Level for a VLIW DSP Processor","author":"muresan","year":"2001","journal-title":"Proc 14th Int Symp System Synthesis"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/371254.371262"},{"key":"ref1","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337786"}],"event":{"name":"3rd IEEE International Workshop on System-on-Chip for Real-Time Applications","acronym":"IWSOC-03","location":"Calgary, Alta., Canada"},"container-title":["The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8609\/27279\/01212997.pdf?arnumber=1212997","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T00:04:51Z","timestamp":1497571491000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1212997\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iwsoc.2003.1212997","relation":{},"subject":[]}}