{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T17:42:33Z","timestamp":1725471753415},"reference-count":3,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iwsoc.2004.1319843","type":"proceedings-article","created":{"date-parts":[[2004,9,28]],"date-time":"2004-09-28T13:50:22Z","timestamp":1096379422000},"page":"23-26","source":"Crossref","is-referenced-by-count":0,"title":["Beyond P-cell and gate-level: accuracy requirements for simulation of nanometer SoC design"],"prefix":"10.1109","author":[{"given":"B.","family":"Marshall","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","article-title":"LVS-parasitic extraction link","author":"ferguson","year":"2003","journal-title":"White Paper"},{"journal-title":"IC\/ASIC Design Closure Study","year":"2001","key":"2"},{"journal-title":"IC\/ASIC Design Closure Study","year":"2001","key":"1"}],"event":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","acronym":"IWSOC-04","location":"Banff, Alta., Canada"},"container-title":["4th IEEE International Workshop on System-on-Chip for Real-Time Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9224\/29242\/01319843.pdf?arnumber=1319843","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T18:41:04Z","timestamp":1489430464000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1319843\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":3,"URL":"https:\/\/doi.org\/10.1109\/iwsoc.2004.1319843","relation":{},"subject":[]}}