{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T20:32:28Z","timestamp":1725481948981},"reference-count":10,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iwsoc.2004.1319855","type":"proceedings-article","created":{"date-parts":[[2004,9,28]],"date-time":"2004-09-28T09:50:22Z","timestamp":1096365022000},"page":"83-86","source":"Crossref","is-referenced-by-count":0,"title":["Using integer equations to check PSL properties in RT level design"],"prefix":"10.1109","author":[{"given":"B.","family":"Alizadeh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Z.","family":"Navabi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/307988.307989"},{"key":"2","article-title":"Taylor expansion diagrams: A compact canonical representation for arithmetic expressions","author":"ciesielski","year":"0","journal-title":"DATE 2002"},{"key":"10","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-61474-5_95","article-title":"VIS: A system for verification and synthesis","author":"brayton","year":"1996","journal-title":"Proc Eighth Conf Computer-Aided Verification"},{"year":"0","key":"1"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2002.995022"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2000.855289"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3184-2"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3190-6"},{"key":"9","article-title":"Intermediate format standardization: Ambiguities, deficiencies, portability issues, documentation and improvements","author":"reshadi","year":"2000","journal-title":"HDLCon2000"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2003.1194711"}],"event":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","acronym":"IWSOC-04","location":"Banff, Alta., Canada"},"container-title":["4th IEEE International Workshop on System-on-Chip for Real-Time Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9224\/29242\/01319855.pdf?arnumber=1319855","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,8,8]],"date-time":"2018-08-08T06:07:39Z","timestamp":1533708459000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1319855\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iwsoc.2004.1319855","relation":{},"subject":[]}}