{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T06:54:57Z","timestamp":1775458497572,"version":"3.50.1"},"reference-count":96,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2011,3,1]],"date-time":"2011-03-01T00:00:00Z","timestamp":1298937600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Emerg. Sel. Topics Circuits Syst."],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/jetcas.2011.2135630","type":"journal-article","created":{"date-parts":[[2011,4,15]],"date-time":"2011-04-15T23:57:33Z","timestamp":1302911853000},"page":"30-41","source":"Crossref","is-referenced-by-count":61,"title":["Robust System Design to Overcome CMOS Reliability Challenges"],"prefix":"10.1109","volume":"1","author":[{"given":"Subhasish","family":"Mitra","sequence":"first","affiliation":[]},{"given":"Kevin","family":"Brelsford","sequence":"additional","affiliation":[]},{"given":"Young Moon","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Hsiao-Heng Kelin","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Yanjing","family":"Li","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629995"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1676055"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837367"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030595"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2007.21"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2004.05.023"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424295"},{"key":"ref39","first-page":"93","article-title":"Managing process variations in Intel's 45 nm CMOS technology","volume":"12","author":"kuhn","year":"2008","journal-title":"Intel Technol J"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.54"},{"key":"ref38","author":"kogge","year":"2008","journal-title":"ExaScale Computing Study Technology Challenges in Achieving Exascale Systems"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1147\/rd.523.0275"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1109\/54.825675"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523231"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146915"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700583"},{"key":"ref30","article-title":"IBM journal research and development","volume":"52","year":"2008","journal-title":"Soft Errors in Circuits and Syst"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/23.490909"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560326"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469615"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837278"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837280"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373464"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003566"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456958"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699215"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700614"},{"key":"ref27","first-page":"131","article-title":"Intel's 45 nm CMOS technology","volume":"12","author":"hicks","year":"2008","journal-title":"Intel Technology J"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894237"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/24.994913"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676475"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/12.980007"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2005.860684"},{"key":"ref69","doi-asserted-by":"crossref","first-page":"373","DOI":"10.1145\/1391469.1391569","article-title":"ifra: instruction footprint recording and analysis for post-silicon bug localization in processors","author":"sung-boem park","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700619"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.22"},{"key":"ref20","first-page":"1","article-title":"A platform 2015 model: Recognition, mining and synthesis moves computers to the era of tera","author":"dubey","year":"2005","journal-title":"Technology at Intel"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1994.292318"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510844"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560329"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1993.470686"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837279"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805803"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.859577"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796528"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.887832"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2008810"},{"key":"ref92","article-title":"Addressing post-silicon validation challenge: Leverage validation &#38; test synergy (invited address)","author":"yerramilli","year":"2006","journal-title":"Proc Int Test Conf"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.557138"},{"key":"ref90","first-page":"671","article-title":"Towards achieving relentless reliability gains in a server marketplace of teraflops, laptops, kilowatts, and &#x201C;cost, cost, cost&#x201D;<formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\ldots$<\/tex> <\/formula>: Making peace between a black art and the bottom line","author":"van horn","year":"2005","journal-title":"Proc Int Test Conf"},{"key":"ref96","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280814"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456961"},{"key":"ref58","first-page":"436","article-title":"Imperfection-immune VLSI logic circuits using carbon nanotube FETs","author":"mitra","year":"2009","journal-title":"Proc Design Automation and Test in Europe"},{"key":"ref57","first-page":"1","article-title":"Combinational logic soft error correction","author":"mitra","year":"2006","journal-title":"Proc Int Test Conf"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.70"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.823341"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894311"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2100531"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457140"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/23.556880"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796494"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456960"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584030"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.556983"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.55"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2010.5488831"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2009.5173324"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2008.61"},{"key":"ref17","year":"0","journal-title":"Amazon Outage Due to Hardware Not Hackers"},{"key":"ref84","year":"2011","journal-title":"OpenSPARC T2 processor"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456959"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364501"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2003.813129"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2007.4299573"},{"key":"ref89","year":"0","journal-title":"PayPal Outage Hits eBay Merchants"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234286"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2005.1493141"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2008.4558930"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771785"},{"key":"ref8","first-page":"12","article-title":"Non-stop advanced architecture","author":"bernick","year":"2005","journal-title":"Proc Int Conf Dependable Systems and Networks"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373409"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2008.2009115"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2002.996639"},{"key":"ref87","first-page":"112","article-title":"Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance","author":"tschanz","year":"2009","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref88","first-page":"282","article-title":"A 45 nm resilient and adaptive microprocessor core for dynamic variation tolerance","author":"tschanz","year":"2010","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"ref46","first-page":"232","article-title":"Concurrent autonomous self-test for uncore components in system-on-chips","author":"li","year":"2010","journal-title":"Proc IEEE VLSI Test Symp"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687436"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/12.2145"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1676066"},{"key":"ref42","first-page":"203","article-title":"LEAP: Layout design through error-aware placement for soft-error resilient sequential cell design","author":"lee","year":"2010","journal-title":"Proc Int Rel Phys Symp"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1387329"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484786"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457059"}],"container-title":["IEEE Journal on Emerging and Selected Topics in Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5503868\/5772128\/05751208.pdf?arnumber=5751208","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:12Z","timestamp":1633909932000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5751208\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":96,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jetcas.2011.2135630","relation":{},"ISSN":["2156-3357","2156-3365"],"issn-type":[{"value":"2156-3357","type":"print"},{"value":"2156-3365","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,3]]}}}