{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,4]],"date-time":"2024-07-04T09:58:04Z","timestamp":1720087084066},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Emerg. Sel. Topics Circuits Syst."],"published-print":{"date-parts":[[2012,6]]},"DOI":"10.1109\/jetcas.2012.2193837","type":"journal-article","created":{"date-parts":[[2012,6,7]],"date-time":"2012-06-07T18:02:51Z","timestamp":1339092171000},"page":"295-306","source":"Crossref","is-referenced-by-count":15,"title":["Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology"],"prefix":"10.1109","volume":"2","author":[{"given":"Giulia","family":"Beanato","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paolo","family":"Giovannini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alessandro","family":"Cevrero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Panagiotis","family":"Athanasopoulos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Zervas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuksel","family":"Temiz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yusuf","family":"Leblebici","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2008.5388567"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.877252"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2012.6249054"},{"key":"ref32","author":"morrow","year":"2008","journal-title":"Handbook of 3-D Integration Technology and Applications of 3-D Integrated Circuits"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2006.1645677"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2012.6248884"},{"key":"ref37","doi-asserted-by":"crossref","first-page":"306","DOI":"10.1109\/ICCAD.2004.1382591","article-title":"A thermal-driven floorplanning algorithm for 3-D ICs","author":"cong","year":"2004","journal-title":"Proc 2004 IEEE\/ACM Int Conf Computer-Aided Design"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139179"},{"key":"ref35","first-page":"149","article-title":"Design and feasibility of multi-Gb\/s quasi-serial vertical interconnects based on TSVs for 3-D ICs","author":"sun","year":"2010","journal-title":"IEEE\/IFIP VLSI Syst Chip Conf"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672170"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1147\/rd.494.0589"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2009.5306542"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523070"},{"key":"ref12","author":"reinders","year":"2007","journal-title":"Intel Threading Building Blocks"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1145\/1150019.1136497","article-title":"Design and management of 3-D chip multiprocessors using network-in-memory","author":"li","year":"2006","journal-title":"Proc of the 20th Intl Symp on Computer Architecture"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168873"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457230"},{"key":"ref17","first-page":"1","article-title":"An optimized 3-D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth","author":"woo","year":"2010","journal-title":"Proc IEEE Int Symp High-Performance Computer Architecture"},{"key":"ref18","first-page":"453","article-title":"3-D-Stacked memory architectures for multi-core processors","author":"loh","year":"2008","journal-title":"Proc of the 20th Intl Symp on Computer Architecture"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034408"},{"key":"ref28","year":"0"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2009.27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSSE.2007.4294463"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0491"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074070"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"404","DOI":"10.1007\/978-3-540-92990-1_29","article-title":"Parallel H.264 decoding on an embedded multicore processor","author":"azevedo","year":"2009","journal-title":"Proc Int Conf High-Performance Embedded Architectures Compilers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1465482.1465560"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/42411.42415"},{"key":"ref2","first-page":"562","article-title":"Interconnects in the third dimension: Design challenges for 3-D ICs","author":"bernstein","year":"2007","journal-title":"Proc 40th ACM\/IEEE Design Automation Conf"},{"key":"ref9","article-title":"From a few cores to many: A tera-scale computing research review","author":"held","year":"0","journal-title":"Intel White Paper"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.60"},{"key":"ref20","year":"0"},{"key":"ref22","first-page":"1","article-title":"Design and analysis of 3-D-MAPS: A many-core 3-D processor with stacked memory","author":"healy","year":"2010","journal-title":"IEEE Custom Integrated Circuits Conf"},{"key":"ref21","first-page":"1","article-title":"3-D embedded multi-core: Some perspectives","author":"clermidy","year":"2011","journal-title":"Design Automat Test Eur Conf Exhibit"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"159","DOI":"10.1145\/1366230.1366261","article-title":"A modular 3-D processor for flexible product design and technology migration","author":"loh","year":"2008","journal-title":"Proc 5th Conf Comput Frontiers"},{"key":"ref23","article-title":"Design and test of 3-D-MAPS, a 3-D die-stack many-core processor","author":"lewis","year":"2010","journal-title":"1st IEEE Int Workshop Testing Three-Dimensional Stacked Integrated Circ (poster)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127915"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457087"}],"container-title":["IEEE Journal on Emerging and Selected Topics in Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5503868\/6213508\/06197726.pdf?arnumber=6197726","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,17]],"date-time":"2022-01-17T01:03:42Z","timestamp":1642381422000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6197726\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6]]},"references-count":40,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/jetcas.2012.2193837","relation":{},"ISSN":["2156-3357","2156-3365"],"issn-type":[{"value":"2156-3357","type":"print"},{"value":"2156-3365","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,6]]}}}