{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,20]],"date-time":"2025-12-20T22:17:44Z","timestamp":1766269064011},"reference-count":50,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2016,9,1]],"date-time":"2016-09-01T00:00:00Z","timestamp":1472688000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Emerg. Sel. Topics Circuits Syst."],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/jetcas.2016.2547738","type":"journal-article","created":{"date-parts":[[2016,4,6]],"date-time":"2016-04-06T20:07:15Z","timestamp":1459973235000},"page":"373-384","source":"Crossref","is-referenced-by-count":17,"title":["Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias"],"prefix":"10.1109","volume":"6","author":[{"given":"Toshiaki","family":"Kirihata","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John","family":"Golz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthew","family":"Wordeman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pooja","family":"Batra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gary W.","family":"Maier","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Norman","family":"Robson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Troy L.","family":"Graves-abe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Berger","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Subramanian S.","family":"Iyer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1002\/9783527644223.ch7"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-6037-1_2"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2014.7028246"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2014.6897355"},{"key":"ref31","article-title":"A fine pitch MEMS probe card with built in active device for 3D IC test","author":"namburi","year":"2013","journal-title":"IEEE SWTW"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176900"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-76534-1"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/LTB-3D.2012.6238091"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea4020077"},{"key":"ref34","first-page":"1","article-title":"Three-dimensional wafer stacking using Cu TSV integrated with 45 nm high performance SOI-CMOS embedded DRAM technology","author":"batra","year":"2013","journal-title":"IEEE S3S"},{"key":"ref28","article-title":"A 0.039 mm2 high performance eDRAM cell based on 32 nm high-<formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm K}$<\/tex><\/formula>\/metal SOI technology","author":"butt","year":"2010","journal-title":"IEEE IEDM Dig Tech Papers"},{"key":"ref27","article-title":"A 45 nm SOI compiled embedded DRAM with random cycles down to 1.3 ns","author":"jacunski","year":"2010","journal-title":"IEEE CICC Dig Tech Papers"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176968"},{"key":"ref2","year":"0"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.521.0199"},{"key":"ref20","first-page":"3.8.1","article-title":"High-performance 14 nm SOI FinFET CMOS tchnology with 0.0174 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu {\\rm m}^2$<\/tex><\/formula> embedded DRAM and 15 levels of Cu metallization","author":"lin","year":"2014","journal-title":"IEEE IEDM Dig Tech Papers"},{"key":"ref22","first-page":"496","article-title":"A 1.2 V 12.8 GB\/s 2 Gb mobile Wide-I\/O DRAM with 4<formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\,\\times\\,$<\/tex> <\/formula>128 I\/Os using TSV-based stacking","author":"kimet","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref21","first-page":"130","article-title":"8 Gb 3D DDR3 SDRAM using through-silicon-via technology","author":"kanget","year":"2009","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref24","article-title":"Hybrid memory cube","volume":"23","author":"pawlowski","year":"2011","journal-title":"Hot Chips"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"ref26","first-page":"228","article-title":"3D Stackable 32 nm high-<formula formulatype=\"inline\"> <tex Notation=\"TeX\">${\\rm K}$<\/tex><\/formula>\/metal gate SOI embedded DRAM prototype","author":"golz","year":"2011","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref25","first-page":"492","article-title":"A 1.2 V 8 Gb 8-channel 128 GB\/s High-Bandwidth-Memory (HBM) stacked DRAM with effective microbump I\/O test methods using 29 nm process and TSV","author":"lee","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2193840"},{"key":"ref10","first-page":"25","author":"lu","year":"2007","journal-title":"3D Integration Why? What? Who?"},{"key":"ref11","article-title":"System scaling technology (Tutorial)","author":"kirihata","year":"2015","journal-title":"7th IEEE Int Memory Workshop"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1002\/9783527644223.ch10"},{"key":"ref12","article-title":"Three dimensional dynamic access memories","author":"kirihata","year":"2014","journal-title":"IEEE International Workshop on Low Temperature Bonding for 3D Integration"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131504"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2012.6263027"},{"key":"ref15","first-page":"14.6.1","article-title":"Through silicon via (TSV) effects on devices in close proximity?The role of mobile ion penetration?Characterization and mitigation","author":"kothandaraman","year":"2014","journal-title":"IEEE IEDM Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796762"},{"key":"ref17","first-page":"336","article-title":"2.5D\/3D TSV processes development and assembly\/packaging technology","author":"wook","year":"2011","journal-title":"Proc IEEE 13th Electron Packag Technol Conf"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2009.5306551"},{"key":"ref19","first-page":"19.4.1","article-title":"0.026 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu {\\rm m}^{2}$<\/tex><\/formula> high performance Embedded DRAM in 22 nm technology for server and SOC applications","author":"pei","year":"0","journal-title":"2014 Int Electron Device Meet Digest"},{"key":"ref4","first-page":"104","article-title":"Steamroller: An x86?64 core implemented in 28 nm bulk CMOS","author":"gillespie","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref3","first-page":"102","article-title":"Ivytown: A 22 nm 15-core enterprise xeon processor family","author":"rusu","year":"2014","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2084470"},{"key":"ref5","first-page":"70","article-title":"22 nm next-generation IBM system z microprocessor","author":"warnock","year":"2015","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref8","first-page":"316","article-title":"A 14 nm 1.1 Mb embedded DRAM with 1 ns access","author":"fredeman","year":"2015","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref7","first-page":"295","author":"kirihata","year":"0","journal-title":"CMOS Processors and Memories"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658450"},{"key":"ref9","article-title":"Three dementia integration?Considerations for memory applications","author":"iyer","year":"2011","journal-title":"IEEE CICC Dig Tech Papers"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.207"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.89"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/2792982"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840407"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/4.499733"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1002\/9783527644223.ch9"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2541228.2541239"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815980"}],"container-title":["IEEE Journal on Emerging and Selected Topics in Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5503868\/7563911\/07448482.pdf?arnumber=7448482","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:02:43Z","timestamp":1642003363000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7448482\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":50,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jetcas.2016.2547738","relation":{},"ISSN":["2156-3357","2156-3365"],"issn-type":[{"value":"2156-3357","type":"print"},{"value":"2156-3365","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,9]]}}}