{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T18:22:16Z","timestamp":1775067736912,"version":"3.50.1"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2016,9,1]],"date-time":"2016-09-01T00:00:00Z","timestamp":1472688000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Emerg. Sel. Topics Circuits Syst."],"published-print":{"date-parts":[[2016,9]]},"DOI":"10.1109\/jetcas.2016.2547779","type":"journal-article","created":{"date-parts":[[2016,4,20]],"date-time":"2016-04-20T18:23:16Z","timestamp":1461176596000},"page":"319-329","source":"Crossref","is-referenced-by-count":55,"title":["Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays"],"prefix":"10.1109","volume":"6","author":[{"given":"Ashwin","family":"Chintaluri","sequence":"first","affiliation":[]},{"given":"Helia","family":"Naeimi","sequence":"additional","affiliation":[]},{"given":"Suriyaprakash","family":"Natarajan","sequence":"additional","affiliation":[]},{"given":"Arijit","family":"Raychowdhury","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2275082"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2010.31"},{"key":"ref12","first-page":"256","article-title":"Defect oriented fault analysis for SRAM","author":"huang","year":"2003","journal-title":"Proc 12th Asian Test Symp"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011170"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.66"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818762"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.206"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116247"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2009.23"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3727\/46\/13\/139601"},{"key":"ref4","first-page":"296","article-title":"A 45 nm 1 Mb embedded STT-MRAM with design techniques to minimize read-disturbance","author":"kim","year":"2011","journal-title":"Proc 2011 Symp VLSI Circuits Dig"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3727\/46\/7\/074003"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424242"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/ISSCC.2015.7062963","article-title":"A 3.3 ns-access-time <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$71.2~\\mu{\\rm W\/MHz}$<\/tex><\/formula> 1 Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture","author":"noguchi","year":"2015","journal-title":"Proc 2015 IEEE Int Solid State Circuits Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2182053"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391540"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2224256"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105370"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2064150"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2027907"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.62.570"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2010.2043645"},{"key":"ref24","year":"0","journal-title":"Predictive Technology Model"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703416"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/54.199799"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386963"}],"container-title":["IEEE Journal on Emerging and Selected Topics in Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5503868\/7563911\/07457326.pdf?arnumber=7457326","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:02:42Z","timestamp":1642003362000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7457326\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9]]},"references-count":26,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jetcas.2016.2547779","relation":{},"ISSN":["2156-3357","2156-3365"],"issn-type":[{"value":"2156-3357","type":"print"},{"value":"2156-3365","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,9]]}}}