{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T18:35:44Z","timestamp":1740162944347,"version":"3.37.3"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T00:00:00Z","timestamp":1559347200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Emerg. Sel. Topics Circuits Syst."],"published-print":{"date-parts":[[2019,6]]},"DOI":"10.1109\/jetcas.2019.2914355","type":"journal-article","created":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T20:07:08Z","timestamp":1556741228000},"page":"346-357","source":"Crossref","is-referenced-by-count":6,"title":["iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric"],"prefix":"10.1109","volume":"9","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5980-4236","authenticated-orcid":false,"given":"Chixiao","family":"Chen","sequence":"first","affiliation":[]},{"given":"Xindi","family":"Liu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5855-2228","authenticated-orcid":false,"given":"Huwan","family":"Peng","sequence":"additional","affiliation":[]},{"given":"Hongwei","family":"Ding","sequence":"additional","affiliation":[]},{"given":"C.-J.","family":"Richard Shi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"},{"journal-title":"A hardware-software blueprint for flexible deep learning specialization","year":"2018","author":"moreau","key":"ref33"},{"journal-title":"Computer Architecture A Quantitative Approach","year":"2011","author":"hennessy","key":"ref32"},{"key":"ref31","first-page":"166","article-title":"Laika: A 5 uW programmable LSTM accelerator for always-on keyword spotting in 65 nm CMOS","author":"giraldo","year":"2018","journal-title":"Proc IEEE European Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00474"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.29"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173176"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2865489"},{"journal-title":"Eyeriss v2 A flexible and high-performance accelerator for emerging deep neural networks","year":"2018","author":"chen","key":"ref34"},{"journal-title":"DoReFa-Net Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients","year":"2016","author":"zhou","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2778281"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310262"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310168"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001179"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2636225"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2764045"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2018.8494327"},{"journal-title":"The RISC-V Instruction Set Manual","year":"0","author":"waterman","key":"ref19"},{"journal-title":"YOLOv3 An Incremental Improvement","year":"2018","author":"redmon","key":"ref28"},{"key":"ref4","first-page":"242","article-title":"14.3 A 28 nm SoC with a 1.2 GHz 568nJ\/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications","author":"whatmough","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"journal-title":"Network in Network","year":"2013","author":"lin","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2017.8094575"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"journal-title":"Mobilenets Efficient convolutional neural networks for mobile vision applications","year":"2017","author":"howard","key":"ref29"},{"key":"ref5","first-page":"1","article-title":"Understanding the limitations of existing energy-efficient design approaches for deep neural networks","author":"chen","year":"2018","journal-title":"Proc SysML Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00037"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080244"},{"key":"ref2","first-page":"1","article-title":"A 1.40 mm2 141 mW 898 GOPS sparse neuromorphic processor in 40 nm CMOS","author":"knag","year":"2016","journal-title":"Proc IEEE Symp VLSI Circuits (VLSI)"},{"key":"ref9","first-page":"1","article-title":"Deep learning: Practice and trends","author":"freitas","year":"2017","journal-title":"Proc Neural Inf Process Syst Conf (NIPS)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/nature14539"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2018.2852780"},{"journal-title":"TVM An automated end-to-end optimizing compiler for deep learning","year":"2018","author":"chen","key":"ref22"},{"journal-title":"Batch Normalization Accelerating Deep Network Training by Reducing Internal Covariate Shift","year":"2015","author":"ioffe","key":"ref21"},{"journal-title":"Very Deep Convolutional Networks for Large-scale Image Recognition","year":"2014","author":"simonyan","key":"ref24"},{"journal-title":"NVIDIA Deep Learning Accelerator","year":"0","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196049"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.54"}],"container-title":["IEEE Journal on Emerging and Selected Topics in Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5503868\/8734723\/08703813.pdf?arnumber=8703813","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:55:00Z","timestamp":1657745700000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8703813\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,6]]},"references-count":38,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/jetcas.2019.2914355","relation":{},"ISSN":["2156-3357","2156-3365"],"issn-type":[{"type":"print","value":"2156-3357"},{"type":"electronic","value":"2156-3365"}],"subject":[],"published":{"date-parts":[[2019,6]]}}}