{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,19]],"date-time":"2026-01-19T09:44:56Z","timestamp":1768815896920,"version":"3.49.0"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"C-BRIC"},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation (SRC) program sponsored by DARPA","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100006234","name":"Sandia National Laboratories","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006234","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Vannevar Bush Faculty Fellowship"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Emerg. Sel. Topics Circuits Syst."],"published-print":{"date-parts":[[2020,9]]},"DOI":"10.1109\/jetcas.2020.3014250","type":"journal-article","created":{"date-parts":[[2020,8,4]],"date-time":"2020-08-04T21:14:02Z","timestamp":1596575642000},"page":"295-305","source":"Crossref","is-referenced-by-count":22,"title":["CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays"],"prefix":"10.1109","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9999-9085","authenticated-orcid":false,"given":"Amogh","family":"Agrawal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6377-6701","authenticated-orcid":false,"given":"Adarsh","family":"Kosta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9713-5400","authenticated-orcid":false,"given":"Sangamesh","family":"Kodge","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7251-1289","authenticated-orcid":false,"given":"Dong Eun","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0735-9695","authenticated-orcid":false,"given":"Kaushik","family":"Roy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2013.2296777"},{"key":"ref33","article-title":"TiM-DNN: Ternary in-memory accelerator for deep neural networks","author":"jain","year":"2019","journal-title":"arXiv 1909 06892"},{"key":"ref32","first-page":"242","article-title":"15.3 a 351TOPS\/W and 372.4GOPS compute-in-memory SRAM macro in 7nm FinFET CMOS for machine-learning applications","author":"dong","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2987714"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899730"},{"key":"ref37","article-title":"X-CHANGR: Changing memristive crossbar mapping for mitigating line-resistance induced accuracy degradation in deep neural networks","author":"agrawal","year":"2019","journal-title":"arXiv 1907 00285"},{"key":"ref36","article-title":"GENIEx: A generalized approach to emulating non-ideality in memristive Xbars using neural networks","author":"chakraborty","year":"2020","journal-title":"arXiv 2003 06902"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2664069"},{"key":"ref34","article-title":"WRPN: Wide reduced-precision networks","author":"mishra","year":"2017","journal-title":"arXiv 1709 01134"},{"key":"ref10","article-title":"Trained ternary quantization","author":"zhu","year":"2016","journal-title":"arXiv 1612 01064"},{"key":"ref40","article-title":"Learning multiple layers of features from tiny images","author":"krizhevsky","year":"2009"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2922889"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2848999"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2841824"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"1009","DOI":"10.1109\/JSSC.2016.2515510","article-title":"A 28 nm configurable memory (TCAM\/BCAM\/SRAM) using push-rule 6T bit cell enabling logic-in-memory","volume":"51","author":"jeloka","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref17","first-page":"160c","article-title":"A 0.3 V VDDmin 4+2T SRAM for searching and in-memory computing using 55nm DDC technology","author":"dong","year":"2017","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008501"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310397"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510687"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2761740"},{"key":"ref6","first-page":"10","article-title":"1.1 Computing&#x2019;s energy problem (and what we can do about it)","author":"horowitz","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2907488"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/359576.359579"},{"key":"ref8","first-page":"525","article-title":"XNOR-Net: ImageNet classification using binary convolutional neural networks","author":"rastegari","year":"2016","journal-title":"Proc Eur Conf Comput Vis"},{"key":"ref7","first-page":"4107","article-title":"Binarized neural networks","author":"hubara","year":"2016","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1038\/505146a"},{"key":"ref9","article-title":"Ternary weight networks","author":"li","year":"2016","journal-title":"arXiv 1605 04711 [cs]"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1561\/9781601982957"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2014.6855225"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/3362035"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662435"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2782087"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7926952"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2981901"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2018.2829522"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TETCI.2018.2829919"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2952773"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3232195.3232226"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2929245"}],"container-title":["IEEE Journal on Emerging and Selected Topics in Circuits and Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/5503868\/9201191\/9158004-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5503868\/9201191\/09158004.pdf?arnumber=9158004","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:52:51Z","timestamp":1649443971000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9158004\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9]]},"references-count":45,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jetcas.2020.3014250","relation":{},"ISSN":["2156-3357","2156-3365"],"issn-type":[{"value":"2156-3357","type":"print"},{"value":"2156-3365","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,9]]}}}