{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,9]],"date-time":"2026-01-09T21:09:30Z","timestamp":1767992970107,"version":"3.49.0"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T00:00:00Z","timestamp":1638316800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T00:00:00Z","timestamp":1638316800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Emerg. Sel. Topics Circuits Syst."],"published-print":{"date-parts":[[2021,12]]},"DOI":"10.1109\/jetcas.2021.3121687","type":"journal-article","created":{"date-parts":[[2021,12,13]],"date-time":"2021-12-13T21:04:58Z","timestamp":1639429498000},"page":"762-775","source":"Crossref","is-referenced-by-count":2,"title":["Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators"],"prefix":"10.1109","volume":"11","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7689-7526","authenticated-orcid":false,"given":"Md Shazzad","family":"Hossain","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4230-1795","authenticated-orcid":false,"given":"Ioannis","family":"Savidis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","article-title":"MobileNets: Efficient convolutional neural networks for mobile vision applications","author":"howard","year":"2017","journal-title":"arXiv 1704 04861"},{"key":"ref38","first-page":"1","article-title":"A reverse write assist circuit for SRAM dynamic write VMIN tracking using Canary SRAMs","author":"banerjee","year":"2014","journal-title":"Proc Int Symp Quality Electronic Design"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080254"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2018.8640161"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2638465"},{"key":"ref37","first-page":"210","article-title":"A low-power and high-performance 10 nm SRAM architecture for mobile applications","author":"clinton","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218676"},{"key":"ref35","article-title":"SCALE-sim: Systolic CNN accelerator simulator","author":"samajdar","year":"2018","journal-title":"arXiv 1811 02883"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3021397"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382127"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001177"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2935251"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2654822.2541967"},{"key":"ref17","author":"fick","year":"2018","journal-title":"Analog Computation in Flash Memory for Datacenter-Scale AI Inference in a Small Chip"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.115"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837451"},{"key":"ref4","first-page":"1","article-title":"Accurate and efficient 2-bit quantized neural networks","author":"choi","year":"2019","journal-title":"Proc Syst Mach Learn (SysML) Conf"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2896794"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2018.8573527"},{"key":"ref27","first-page":"230","article-title":"A 4.6 GHz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry","author":"karl","year":"2012","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000459"},{"key":"ref5","first-page":"1","article-title":"Ultra-low precision 4-bit training of deep neural networks","volume":"33","author":"sun","year":"2020","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173177"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.54"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00016"},{"key":"ref1","year":"2020","journal-title":"Edge Computing Market Size Share and Trends Analysis Report"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2020.3009924"},{"key":"ref20","first-page":"55","article-title":"SRAM leakage suppression by minimizing standby supply voltage","author":"qin","year":"2004","journal-title":"Proc IEEE Int Symp Quality Electron Design"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2939682"},{"key":"ref21","first-page":"242","article-title":"A 351 TOPS\/W and 372.4 GOPS compute-in-memory SRAM macro in 7 nm FinFET CMOS for machine-learning applications","author":"dong","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2020.104782"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702425"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3370748.3406558"},{"key":"ref25","first-page":"432","article-title":"FIVR-fully integrated voltage regulators on 4th generation Intel Core SoCs","author":"burton","year":"2014","journal-title":"Proc IEEE Appl Power Electron Conf Expo (APEC)"}],"container-title":["IEEE Journal on Emerging and Selected Topics in Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5503868\/9647029\/09583252.pdf?arnumber=9583252","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T21:36:18Z","timestamp":1647293778000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9583252\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12]]},"references-count":39,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jetcas.2021.3121687","relation":{},"ISSN":["2156-3357","2156-3365"],"issn-type":[{"value":"2156-3357","type":"print"},{"value":"2156-3365","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,12]]}}}