{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,27]],"date-time":"2026-05-27T23:31:48Z","timestamp":1779924708298,"version":"3.53.1"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62171313"],"award-info":[{"award-number":["62171313"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["U21B2031"],"award-info":[{"award-number":["U21B2031"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Emerg. Sel. Topics Circuits Syst."],"published-print":{"date-parts":[[2024]]},"DOI":"10.1109\/jetcas.2024.3460792","type":"journal-article","created":{"date-parts":[[2024,9,16]],"date-time":"2024-09-16T18:02:57Z","timestamp":1726509777000},"page":"1-1","source":"Crossref","is-referenced-by-count":3,"title":["Modeling the Effect of SEUs on the Configuration Memory of SRAM-FPGA based CNN Accelerators"],"prefix":"10.1109","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9887-1418","authenticated-orcid":false,"given":"Zhen","family":"Gao","sequence":"first","affiliation":[{"name":"School of Electrical and Information Engineering, Tianjin University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiaqi","family":"Feng","sequence":"additional","affiliation":[{"name":"School of Electrical and Information Engineering, Tianjin University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shihui","family":"Gao","sequence":"additional","affiliation":[{"name":"School of Electrical and Information Engineering, Tianjin University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1375-0508","authenticated-orcid":false,"given":"Qiang","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Tianjin University, Tianjin, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Guangjun","family":"Ge","sequence":"additional","affiliation":[{"name":"School of Electronic Engineering, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2931-8958","authenticated-orcid":false,"given":"Yu","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Electronic Engineering, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2540-5234","authenticated-orcid":false,"given":"Pedro","family":"Reviriego","sequence":"additional","affiliation":[{"name":"ETSI de Telecomunicación, Universidad Politécnica de Madrid, Madrid, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","article-title":"Very deep convolutional networks for large-scale image recognition","volume-title":"Proc. ICLR","author":"Simonyan"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2705069"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2939726"},{"key":"ref5","volume-title":"Road Vehicles\u2014Functional Safety","year":"2011"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6715-2"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-31069-5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2033381"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS47505.2019.000-8"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465834"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2018.2884460"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2021.3050707"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2018.8347234"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3046075"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2023.3235767"},{"key":"ref16","volume-title":"Application Note: Triple Module Redundancy Design Techniques for Virtex FPGAs","author":"Carmichael","year":"2006"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DSN-W.2017.47"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ITC44170.2019.9000149"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.3043449"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2981056"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2930577"},{"key":"ref22","volume-title":"Zynq DPU v3.2-Product Guide, PG338 (v3.2)","year":"2020"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2021.3131346"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2004.839516"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176466"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2456101"},{"key":"ref27","volume-title":"UG909 (V2018.3) Vivado Design Suite User Guide Partial Reconfiguration","year":"2028"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344729"},{"key":"ref29","volume-title":"7 Series DSP48E1 Slice User Guide (UG479)","year":"2023"},{"key":"ref30","volume-title":"Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)","year":"2023"},{"key":"ref31","volume-title":"UltraScale Architecture Configurable Logic Block User Guide, UG574 (V1.5)","year":"2017"}],"container-title":["IEEE Journal on Emerging and Selected Topics in Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/5503868\/5751207\/10680513.pdf?arnumber=10680513","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,14]],"date-time":"2024-12-14T06:48:12Z","timestamp":1734158892000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10680513\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/jetcas.2024.3460792","relation":{},"ISSN":["2156-3357","2156-3365"],"issn-type":[{"value":"2156-3357","type":"print"},{"value":"2156-3365","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024]]}}}