{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,24]],"date-time":"2025-12-24T18:52:10Z","timestamp":1766602330514,"version":"3.48.0"},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2025,12,1]],"date-time":"2025-12-01T00:00:00Z","timestamp":1764547200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,12,1]],"date-time":"2025-12-01T00:00:00Z","timestamp":1764547200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,12,1]],"date-time":"2025-12-01T00:00:00Z","timestamp":1764547200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2022YFB2803405"],"award-info":[{"award-number":["2022YFB2803405"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Emerg. Sel. Topics Circuits Syst."],"published-print":{"date-parts":[[2025,12]]},"DOI":"10.1109\/jetcas.2025.3590870","type":"journal-article","created":{"date-parts":[[2025,7,21]],"date-time":"2025-07-21T18:09:12Z","timestamp":1753121352000},"page":"537-545","source":"Crossref","is-referenced-by-count":0,"title":["BUP: A Deadlock Resolution Framework for 2.5D Chiplet Networks by Update Packet Bypassing"],"prefix":"10.1109","volume":"15","author":[{"given":"Tiejun","family":"Li","sequence":"first","affiliation":[{"name":"College of Computer Science and Technology, National University of Defense Technology, Changsha, Hunan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1008-4805","authenticated-orcid":false,"given":"Jianmin","family":"Zhang","sequence":"additional","affiliation":[{"name":"College of Computer Science and Technology, National University of Defense Technology, Changsha, Hunan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yi","family":"Yang","sequence":"additional","affiliation":[{"name":"College of Computer Science and Technology, National University of Defense Technology, Changsha, Hunan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yan","family":"Sun","sequence":"additional","affiliation":[{"name":"College of Computer Science and Technology, National University of Defense Technology, Changsha, Hunan, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749724"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.8"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.44"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2019.2910249"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358255"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00044"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00063"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00074"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00066"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3029682"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774617"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00076"},{"key":"ref13","article-title":"The gem5 simulator","author":"Lowe-Power","year":"2020","journal-title":"arXiv:2007.03152"},{"key":"ref14","first-page":"978","article-title":"Pre-bond testing of the silicon interposer in 2.5D ICs","volume-title":"Proc. Design, Autom. Test Eur. Conf. Exhib. (DATE)","author":"Wang"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/71.877831"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3053277.3053279"}],"container-title":["IEEE Journal on Emerging and Selected Topics in Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/5503868\/11313699\/11087214.pdf?arnumber=11087214","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,24]],"date-time":"2025-12-24T18:46:29Z","timestamp":1766601989000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11087214\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,12]]},"references-count":17,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jetcas.2025.3590870","relation":{},"ISSN":["2156-3357","2156-3365"],"issn-type":[{"type":"print","value":"2156-3357"},{"type":"electronic","value":"2156-3365"}],"subject":[],"published":{"date-parts":[[2025,12]]}}}