{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:57:59Z","timestamp":1780675079041,"version":"3.54.1"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2025,12,1]],"date-time":"2025-12-01T00:00:00Z","timestamp":1764547200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,12,1]],"date-time":"2025-12-01T00:00:00Z","timestamp":1764547200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,12,1]],"date-time":"2025-12-01T00:00:00Z","timestamp":1764547200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Emerg. Sel. Topics Circuits Syst."],"published-print":{"date-parts":[[2025,12]]},"DOI":"10.1109\/jetcas.2025.3591727","type":"journal-article","created":{"date-parts":[[2025,7,22]],"date-time":"2025-07-22T18:05:53Z","timestamp":1753207553000},"page":"648-658","source":"Crossref","is-referenced-by-count":2,"title":["Iterative Layout-Aware Power, Thermal, and IR-Drop Co-Optimization: Ensuring Convergency in 3D-ICs"],"prefix":"10.1109","volume":"15","author":[{"ORCID":"https:\/\/orcid.org\/0009-0006-8202-2159","authenticated-orcid":false,"given":"Mohamed","family":"Naeim","sequence":"first","affiliation":[{"name":"Cadence Design Systems, San Jose, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7912-3692","authenticated-orcid":false,"given":"Dwaipayan","family":"Biswas","sequence":"additional","affiliation":[{"name":"Imec, Leuven, Belgium"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yun","family":"Dai","sequence":"additional","affiliation":[{"name":"Cadence Design Systems, San Jose, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Odysseas","family":"Zografos","sequence":"additional","affiliation":[{"name":"Imec, Leuven, Belgium"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0680-4969","authenticated-orcid":false,"given":"Herman","family":"Oprins","sequence":"additional","affiliation":[{"name":"Imec, Leuven, Belgium"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4975-6672","authenticated-orcid":false,"given":"Geert","family":"Van der Plas","sequence":"additional","affiliation":[{"name":"Imec, Leuven, Belgium"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"C. T.","family":"Kao","sequence":"additional","affiliation":[{"name":"Cadence Design Systems, San Jose, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pinhong","family":"Chen","sequence":"additional","affiliation":[{"name":"Cadence Design Systems, San Jose, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5915-5160","authenticated-orcid":false,"given":"Dragomir","family":"Milojevic","sequence":"additional","affiliation":[{"name":"Bio, Electro, and Mechanical Systems Department (BEAMS), Universit&#x00E9; Libre de Bruxelles, Brussels, Belgium"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593229"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/tdmr.2006.876577"},{"key":"ref3","first-page":"1","article-title":"Single- and multi-voltage IC circuit thermal runaway analysis and application","volume-title":"Proc. 40th SEMI-THERM Symp.","author":"Zhao"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2005.847944"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2017.03.019"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/edtm.2017.7947497"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/itherm51669.2021.9503209"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/jxcdc.2024.3496118"},{"key":"ref9","volume-title":"Voltus IC Power Integrity Solution User Guide","year":"2025"},{"key":"ref10","volume-title":"Celsius Studio User Guide","year":"2025"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-20481-9_10"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055171"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2015.2432141"},{"key":"ref14","first-page":"670","article-title":"Thermal-aware cell and through-silicon-via co-placement for 3D ICs","volume-title":"Proc. 48th ACM\/EDAC\/IEEE Design Autom. Conf. (DAC)","author":"Cong"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/3dic.2016.7970032"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/esserc62670.2024.10719443"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3531437.3539724"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/irps48203.2023.10117979"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/isvlsi61997.2024.00018"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2023.3314135"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/isvlsi61997.2024.00020"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ted.2007.909038"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2014.2380638"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3372780.3378169"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/irps48228.2024.10529355"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/emcsipi50001.2023.10241702"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ectc32862.2020.00046"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ectc51529.2024.00171"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.23919\/date51398.2021.9474087"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/vlsitechnologyandcir46783.2024.10631463"}],"container-title":["IEEE Journal on Emerging and Selected Topics in Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/5503868\/11313699\/11088096.pdf?arnumber=11088096","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,24]],"date-time":"2025-12-24T18:46:28Z","timestamp":1766601988000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11088096\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,12]]},"references-count":30,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jetcas.2025.3591727","relation":{},"ISSN":["2156-3357","2156-3365"],"issn-type":[{"value":"2156-3357","type":"print"},{"value":"2156-3365","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,12]]}}}