{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,20]],"date-time":"2026-05-20T16:10:18Z","timestamp":1779293418865,"version":"3.51.4"},"reference-count":203,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2025,12,1]],"date-time":"2025-12-01T00:00:00Z","timestamp":1764547200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2022YFB4401501"],"award-info":[{"award-number":["2022YFB4401501"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Emerg. Sel. Topics Circuits Syst."],"published-print":{"date-parts":[[2025,12]]},"DOI":"10.1109\/jetcas.2025.3636408","type":"journal-article","created":{"date-parts":[[2025,11,24]],"date-time":"2025-11-24T19:00:36Z","timestamp":1764010836000},"page":"514-536","source":"Crossref","is-referenced-by-count":4,"title":["Survey of Chiplet Technology: SoC Architecture, Interconnect, EDA, and Advanced Packaging"],"prefix":"10.1109","volume":"15","author":[{"given":"Hongwei","family":"Liu","sequence":"first","affiliation":[{"name":"Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5316-619X","authenticated-orcid":false,"given":"Yuan","family":"Du","sequence":"additional","affiliation":[{"name":"Nanjing University, Nanjing, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bo","family":"Pu","sequence":"additional","affiliation":[{"name":"DeTooLIC Technology Company Ltd., Ningbo, Zhejiang, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4864-7677","authenticated-orcid":false,"given":"Guojun","family":"Yuan","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5784-3581","authenticated-orcid":false,"given":"Yuhang","family":"Liu","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Linji","family":"Zheng","sequence":"additional","affiliation":[{"name":"Wuxi Institute of Interconnect Technology, Wuxi, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pengchao","family":"Wang","sequence":"additional","affiliation":[{"name":"Wuxi Institute of Interconnect Technology, Wuxi, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"An","family":"Yang","sequence":"additional","affiliation":[{"name":"Wuxi Institute of Interconnect Technology, Wuxi, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu","family":"Li","sequence":"additional","affiliation":[{"name":"Wuxi Institute of Interconnect Technology, Wuxi, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chengming","family":"Yu","sequence":"additional","affiliation":[{"name":"Wuxi Institute of Interconnect Technology, Wuxi, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fei","family":"Guo","sequence":"additional","affiliation":[{"name":"Wuxi Institute of Interconnect Technology, Wuxi, Jiangsu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9447-8763","authenticated-orcid":false,"given":"Xiaoteng","family":"Zhao","sequence":"additional","affiliation":[{"name":"Key Laboratory of Analog Integrated Circuits, School of Integrated Circuits, Xidian University, Xi&#x2019;an, Shanxi, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8978-6825","authenticated-orcid":false,"given":"Xuqiang","family":"Zheng","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences, Institute of Microelectronics, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"He","family":"Sun","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences, Institute of Microelectronics, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6322-8614","authenticated-orcid":false,"given":"Yongfu","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Micro and Nano Electronics Engineering, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shaolin","family":"Xiang","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1545-1600","authenticated-orcid":false,"given":"Qinfen","family":"Hao","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"Chiplet","year":"2024"},{"key":"ref2","volume-title":"\u2019Moore\u2019s Law\u2019 Predicts the Future of Integrated Circuits","year":"2025"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/iciprm.2010.5516241"},{"key":"ref4","volume-title":"DARPA CHIPS Program Pushes For Chiplets","year":"2017"},{"key":"ref5","volume-title":"Chord Signaling for High-Speed Chip-to-Chip Applications","year":"2025"},{"key":"ref6","volume-title":"Universal Chiplet,  Interconnect Express (UCIe)TM: Building an Open Chiplet Ecosystem Interconnect Express","year":"2025"},{"key":"ref7","volume-title":"Open Chiplet Economy","year":"2025"},{"key":"ref8","volume-title":"Technical Requirements for Chiplet Interface Bus","year":"2023"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2022.3144461"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3658617.3703134"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/jetcas.2024.3445829"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/asp-dac58780.2024.10473961"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-023-3926-8"},{"key":"ref14","volume-title":"IFTLE 545: Chiplet Definition and Standardization","year":"2023"},{"key":"ref15","article-title":"Mozart: A chiplet ecosystem-accelerator codesign framework for composable bespoke application specific integrated circuits","author":"Jin","year":"2025","journal-title":"arXiv:2510.08873"},{"key":"ref16","volume-title":"CoWoS","year":"2024"},{"key":"ref17","volume-title":"AMD 3D V-CacheTM Technology","year":"2025"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530428"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3686310"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/dac18074.2021.9586261"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/mm.2020.3042383"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2018.8310173"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9063103"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063113"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/hcs61935.2024.10665102"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454441"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/hcs61935.2024.10665220"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/mm.2021.3085578"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/isca.2018.00066"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3608098"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/hpca53966.2022.00091"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358302"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2025.3572112"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/hpca53966.2022.00076"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA63168.2024.00042"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2025.3583289"},{"key":"ref37","volume-title":"Standards & Documents Search","year":"2025"},{"key":"ref38","volume-title":"AMD Unveils World\u2019s Most Advanced Gaming Graphics Cards, Built on Groundbreaking AMD RDNA 3 Architecture With Chiplet Design","year":"2022"},{"key":"ref39","volume-title":"Leading the World in High-Speed Connectivity Solutions","year":"2025"},{"key":"ref40","volume-title":"Numem Develops MRAM-based Chiplets","year":"2025"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/3729215"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/dsn58291.2024.00022"},{"issue":"3","key":"ref43","doi-asserted-by":"crossref","first-page":"244","DOI":"10.1038\/s41928-024-01126-y","article-title":"High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express","volume":"7","author":"Das Sharma","year":"2024","journal-title":"Nature Electron."},{"key":"ref44","volume-title":"Arm Chiplet System Architecture","year":"2025"},{"key":"ref45","volume-title":"Ecosystem Collaboration Drives New AMBA Specification for Chiplets","year":"2024"},{"key":"ref46","volume-title":"Neoverse Compute Subsystems V3 (CSS V3)","year":"2025"},{"key":"ref47","volume-title":"Cadence Unveils Arm-Based System Chiplet","year":"2024"},{"key":"ref48","volume-title":"Alphawave Semi and Arm Accelerate Scalable Computing With CSA Chiplets","year":"2025"},{"key":"ref49","article-title":"The survey of chiplet-based integrated architecture: An EDA perspective","author":"Chen","year":"2025","journal-title":"arXiv:2411.04410"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2020.3036341"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/3313231.3352380"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/tcpmt.2019.2953659"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2020.3033136"},{"key":"ref54","volume-title":"DARPA CHIPS Program Overview","year":"2023"},{"key":"ref55","volume-title":"TSMC 3DFabric White Paper","year":"2024"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/mm.2024.3436008"},{"key":"ref57","volume-title":"A Sneak Peek at Chiplet Standards","year":"2023"},{"key":"ref58","volume-title":"Implementation Agreement for a 3.2 Tb\/s Co-Packaged (CPO) Module","year":"2023"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/OJSSCS.2024.3506694"},{"key":"ref60","volume-title":"OpenHBI Specification Version 1.0","year":"2021"},{"key":"ref61","volume-title":"CPO Technology: Applications, Challenges, and Standard Progress","year":"2023"},{"key":"ref62","volume-title":"In-Package Optical I\/O Versus Co-Packaged Optics\u2013Let\u2019s Get Technical!"},{"key":"ref63","volume-title":"What\u2019s Next in AI Starts Here","year":"2025"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2875092"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830174"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49661.2025.10904631"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49661.2025.10904754"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.23919\/vlsicircuits52068.2021.9492439"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2962655"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9366048"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067477"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067395"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631466"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631527"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3338478"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49661.2025.10904767"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3261125"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49657.2024.10454481"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830454"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731740"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454440"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.3390\/mi16080896"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2014.6757501"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3285896"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3330485"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1145\/3665314.3670825"},{"key":"ref87","volume-title":"IA Title: Common Electrical I\/O (CEI)","year":"2024"},{"key":"ref88","volume-title":"OIF Hot Topic Fact Sheet\u2013Common Electrical I\/O (CEI)-112","year":"2024"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731636"},{"key":"ref90","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365975"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365752"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3141802"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631427"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631354"},{"key":"ref95","article-title":"Design methodologies and automated generation of ultra high speed wireline serdes transmitters","author":"Biswas","year":"2023"},{"key":"ref96","article-title":"Feedforward MLSE equalization for high speed serial links","author":"Kwon","year":"2023"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2976067"},{"key":"ref98","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3314446"},{"key":"ref99","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC60305.2024.10848817"},{"key":"ref100","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631547"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1109\/JLT.2024.3402053"},{"key":"ref102","volume-title":"Accelerating Innovation Through A Standard Chiplet Interface: The Advanced Interface Bus (AIB)","year":"2023"},{"key":"ref103","volume-title":"OcDSAOpenHBI Workstream Proposal","year":"2019"},{"key":"ref104","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358255"},{"key":"ref105","volume-title":"High Bandwidth Memory (HBM4) DRAM","year":"2025"},{"key":"ref106","volume-title":"Accelerating Chiplets With 112G XSR SerDes PHYs","year":"2019"},{"key":"ref107","volume-title":"OIF Launches CEI-112G-XSR Project Enabling Intra-Package Interconnects","year":"2018"},{"key":"ref108","volume-title":"OIF Unveils CEI-112G-XSR+_PAM4 Extended Extra Short Reach Implementation Agreement, Paving the Way for Advanced Interconnectivity","year":"2024"},{"key":"ref109","volume-title":"TIM for 3D-Stacked Packages: Vertical Heat Paths and Interface Considerations","year":"2025"},{"key":"ref110","volume-title":"Standard for Chiplet Interface Circuit","year":"2024"},{"key":"ref111","first-page":"1","article-title":"Juniper\u2019s express 5: A 28.8Tbps network routing ASIC and variations","volume-title":"Proc. Hot Chips Symp.","author":"Wu"},{"issue":"6","key":"ref112","first-page":"2582","article-title":"Addressing power and thermal challenges in advanced packaging for AI CPUs\/GPUs: Insights into multi-die stacking technology","volume":"5","author":"Katari","year":"2023","journal-title":"Int. J. Multidisciplinary Res."},{"key":"ref113","volume-title":"High-Speed Chiplet Interface IP Developments and Challenges","author":"Zhou","year":"2023"},{"key":"ref114","volume-title":"Technical Requirements for Chiplet Interface Bus","year":"2023"},{"key":"ref115","volume-title":"Implementation Agreement for the High Bandwidth Coherent Driver Modulator (HB-CDM)","year":"2021"},{"key":"ref116","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI51249.2020.00017"},{"key":"ref117","doi-asserted-by":"publisher","DOI":"10.1109\/ectc.2011.5898527"},{"key":"ref118","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51529.2024.00049"},{"key":"ref119","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM45625.2022.10019517"},{"key":"ref120","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51529.2024.00055"},{"key":"ref121","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2016.201"},{"key":"ref122","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51909.2023.00091"},{"key":"ref123","doi-asserted-by":"publisher","DOI":"10.23919\/vlsitechnologyandcir57934.2023.10185224"},{"key":"ref124","doi-asserted-by":"publisher","DOI":"10.1109\/ectc32696.2021.00034"},{"key":"ref125","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51529.2024.00151"},{"key":"ref126","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2015.7334619"},{"key":"ref127","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2019.00092"},{"key":"ref128","volume-title":"3.5D: The Great Compromise","year":"2024"},{"key":"ref129","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51529.2024.00391"},{"key":"ref130","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51909.2023.00154"},{"key":"ref131","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2023.3256384"},{"key":"ref132","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32862.2020.00013"},{"key":"ref133","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51909.2023.00174"},{"key":"ref134","first-page":"00718","article-title":"Advanced fanout embedded bridge packaging technology for chiplets integration","volume-title":"Proc. 18th Int. Conf. Device Packaging","author":"Cao"},{"key":"ref135","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32696.2021.00320"},{"key":"ref136","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32862.2020.00015"},{"key":"ref137","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32696.2021.00027"},{"key":"ref138","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32696.2021.00348"},{"key":"ref139","doi-asserted-by":"publisher","DOI":"10.1109\/eptc62800.2024.10909677"},{"key":"ref140","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2023.3265529"},{"key":"ref141","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51909.2023.00188"},{"key":"ref142","doi-asserted-by":"publisher","DOI":"10.1007\/s13391-023-00433-4"},{"key":"ref143","doi-asserted-by":"publisher","DOI":"10.3390\/nano13172490"},{"key":"ref144","doi-asserted-by":"publisher","DOI":"10.3390\/polym13213633"},{"key":"ref145","doi-asserted-by":"publisher","DOI":"10.1109\/ectc32862.2020.00234"},{"key":"ref146","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2024.3349669"},{"key":"ref147","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51909.2023.00274"},{"key":"ref148","doi-asserted-by":"publisher","DOI":"10.1109\/hcs55958.2022.9895534"},{"key":"ref149","doi-asserted-by":"publisher","DOI":"10.1109\/mm.2021.3112025"},{"key":"ref150","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3112025"},{"key":"ref151","article-title":"Review performance, efficiency, and cost analysis of wafer-scale AI accelerators","volume":"112","author":"Zhang","year":"2025","journal-title":"Comput. Electr. Eng."},{"key":"ref152","article-title":"Heterogeneous integration on silicon-interconnect fabric using fine-pitch interconnects (<10 \u03bcm)","author":"SivaChandra","year":"2020"},{"key":"ref153","doi-asserted-by":"publisher","DOI":"10.3390\/electronics14132682"},{"key":"ref154","doi-asserted-by":"publisher","DOI":"10.1016\/j.ijheatmasstransfer.2024.126212"},{"key":"ref155","doi-asserted-by":"publisher","DOI":"10.1109\/ectc.2016.165"},{"key":"ref156","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51906.2022.00173"},{"key":"ref157","doi-asserted-by":"publisher","DOI":"10.3390\/nano12193365"},{"key":"ref158","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51906.2022.00197"},{"key":"ref159","doi-asserted-by":"publisher","DOI":"10.1002\/smtd.202301788"},{"key":"ref160","doi-asserted-by":"publisher","DOI":"10.3390\/polym15193895"},{"key":"ref161","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247949"},{"key":"ref162","doi-asserted-by":"publisher","DOI":"10.4071\/001c.129616"},{"key":"ref163","doi-asserted-by":"publisher","DOI":"10.1145\/3477206.3477459"},{"key":"ref164","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2023.3347302"},{"key":"ref165","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2021.3113664"},{"key":"ref166","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA57654.2024.00022"},{"key":"ref167","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00083"},{"key":"ref168","doi-asserted-by":"publisher","DOI":"10.1145\/3529090"},{"key":"ref169","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473888"},{"key":"ref170","article-title":"RLPlanner: Reinforcement learning based floorplan ning for chiplets with fast thermal analysis","author":"Duan","year":"2023","journal-title":"arXiv:2312.16895"},{"key":"ref171","doi-asserted-by":"publisher","DOI":"10.1109\/AINIT65432.2025.11035832"},{"key":"ref172","volume-title":"COMSOL News 2025: Multiphysics Simulation Magazine\u2013Commercializing Fusion Power and Advanced Engineering Applications","year":"2025"},{"key":"ref173","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3321933"},{"key":"ref174","doi-asserted-by":"publisher","DOI":"10.1016\/j.ijheatmasstransfer.2023.124593"},{"key":"ref175","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51529.2024.00284"},{"key":"ref176","doi-asserted-by":"publisher","DOI":"10.1109\/3dic57175.2023.10155000"},{"key":"ref177","volume-title":"Reduce 3DIC Design Complexity With Early Package Assembly Verification","year":"2023"},{"key":"ref178","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2020.3015494"},{"key":"ref179","doi-asserted-by":"publisher","DOI":"10.1109\/ectc51909.2023.00176"},{"key":"ref180","doi-asserted-by":"publisher","DOI":"10.1109\/iedm45625.2022.10019538"},{"key":"ref181","volume-title":"Open Compute Project Foundation and JEDEC Drive Open Silicon Innovation","year":"2025"},{"key":"ref182","volume-title":"Using a Markup Language in Chiplet-Based Design","year":"2023"},{"key":"ref183","volume-title":"GDSII St-ream Format Manual"},{"key":"ref184","volume-title":"Application NoteIBIS\/IBIS\u2013AMI Models: Background and Usage","year":"2017"},{"key":"ref185","volume-title":"Library Exchange Format and Design Exchange Format (LEF\/DEF)","year":"2025"},{"key":"ref186","doi-asserted-by":"publisher","DOI":"10.1145\/3627703.3629583"},{"key":"ref187","volume-title":"Standard for 3Dblox\u2013Chiplet Connectivity and Physical Properties Description Language, PAR Approved","year":"2024"},{"issue":"1","key":"ref188","first-page":"118","article-title":"Hotspots and trends in collaborative research of numerical simulation and multiphysics in 2024: A review","volume":"43","author":"Pu","year":"2025","journal-title":"Sci. Technol.Rev."},{"key":"ref189","article-title":"Design of 2.5 D interposer in high bandwidth memory and through silicon via for high speed signal","volume-title":"IEEE Techrxiv","author":"Pu","year":"2020"},{"key":"ref190","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2024.3365077"},{"key":"ref191","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2023.3336275"},{"key":"ref192","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2022.3156807"},{"key":"ref193","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32862.2020.00306"},{"key":"ref194","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC51909.2023.00239"},{"key":"ref195","doi-asserted-by":"publisher","DOI":"10.1145\/3765905"},{"key":"ref196","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2025.115797"},{"key":"ref197","doi-asserted-by":"publisher","DOI":"10.1109\/iccd65941.2025.00029"},{"key":"ref198","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2024.115530"},{"key":"ref199","doi-asserted-by":"publisher","DOI":"10.3390\/mi14081493"},{"key":"ref200","doi-asserted-by":"publisher","DOI":"10.1109\/WSC48552.2020.9384052"},{"key":"ref201","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3466809"},{"key":"ref202","doi-asserted-by":"publisher","DOI":"10.1109\/ETS61313.2024.10567355"},{"key":"ref203","doi-asserted-by":"publisher","DOI":"10.1109\/PAINE62042.2024.10792842"}],"container-title":["IEEE Journal on Emerging and Selected Topics in Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/5503868\/11313699\/11265742.pdf?arnumber=11265742","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,16]],"date-time":"2026-02-16T21:07:39Z","timestamp":1771276059000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11265742\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,12]]},"references-count":203,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jetcas.2025.3636408","relation":{},"ISSN":["2156-3357","2156-3365"],"issn-type":[{"value":"2156-3357","type":"print"},{"value":"2156-3365","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,12]]}}}