{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,26]],"date-time":"2025-07-26T09:12:27Z","timestamp":1753521147744},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2009,1]]},"DOI":"10.1109\/jproc.2008.2007471","type":"journal-article","created":{"date-parts":[[2009,3,5]],"date-time":"2009-03-05T23:48:05Z","timestamp":1236296885000},"page":"96-107","source":"Crossref","is-referenced-by-count":48,"title":["3-D Technology Assessment: Path-Finding the Technology\/Design Sweet-Spot"],"prefix":"10.1109","volume":"97","author":[{"given":"P.","family":"Marchal","sequence":"first","affiliation":[]},{"given":"B.","family":"Bougard","sequence":"additional","affiliation":[]},{"given":"G.","family":"Katti","sequence":"additional","affiliation":[]},{"given":"M.","family":"Stucchi","sequence":"additional","affiliation":[]},{"given":"W.","family":"Dehaene","sequence":"additional","affiliation":[]},{"given":"A.","family":"Papanikolaou","sequence":"additional","affiliation":[]},{"given":"D.","family":"Verkest","sequence":"additional","affiliation":[]},{"given":"B.","family":"Swinnen","sequence":"additional","affiliation":[]},{"given":"E.","family":"Beyne","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466143"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2003.1194993"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2003.1183348"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.149"},{"key":"ref37","article-title":"d-staf: scalable temperature and leakage aware floor-planning for 3d integrated circuits","author":"zhou","year":"2007","journal-title":"Proc Int Conf Comput Aided Design"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.885831"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870069"},{"key":"ref34","first-page":"450","article-title":"2.5d system integration: a design driven system implementation schema","author":"deng","year":"2004","journal-title":"Proc ASPDAC"},{"key":"ref10","author":"swinnen","year":"0","journal-title":"Wafer Level 3-D ICs Process Technology"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882589"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337394"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/92.902261"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"562","DOI":"10.1145\/1278480.1278623","article-title":"interconnects in the third dimension: design challenges for 3d ics","author":"bernstein","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.873612"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/96.544361"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168873"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.134"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1145\/1150019.1136497","article-title":"design and management of 3d chip multiprocessors using network-in-memory","author":"li","year":"2006","journal-title":"Proc 33rd Ann Int Symp Comput Architect (ISCA 06)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320948"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2005.1441287"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.4108\/ICST.NANONET2007.2033"},{"key":"ref3","article-title":"3d integration of cmos transistors with icv-slid technology","author":"klump","year":"2005","journal-title":"3D Architectures for Semiconductor Integration and Packaging"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2007.373894"},{"key":"ref29","first-page":"15","article-title":"extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs","author":"weerasekera","year":"0","journal-title":"Proc Int Conf Comput Aided Design 2007"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2007.373893"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346786"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2007.373865"},{"key":"ref2","article-title":"3d ic technology: capabilities and applications","author":"guarini","year":"2004","journal-title":"3D Architectures for Semiconductor Integration and Packaging"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2007.382391"},{"key":"ref1","first-page":"85","article-title":"technologies for 3d assembly and chip level stack","author":"bonkohara","year":"2003","journal-title":"Proc 2nd Int Symp Microelectron Packag (ISMP2003 IMAPS-Korea)"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/35.393001"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.138"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/92.974905"},{"key":"ref22","first-page":"519","article-title":"three-dimensional cache design exploration using 3dcacti","author":"tsai","year":"0","journal-title":"Proc IEEE Int Conf Comput Design (ICCD'05)"},{"key":"ref47","article-title":"energy-efficient software-defined radio solutions for mimo-based broadband communication","author":"bougard","year":"2007","journal-title":"Proc Eur Signal Process Conf (EUSIPCO)"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2005.65"},{"key":"ref42","first-page":"682","article-title":"thermal analysis of heterogeneous 3d-ic for various scenarios","author":"chiang","year":"2001","journal-title":"Proc IEDM"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2004.1347939"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.59"},{"key":"ref44","first-page":"991","article-title":"a thermally aware performance analysis of vertically integrated (3d) processor memory hierarchy","author":"loi","year":"2006","journal-title":"Proc 40th Design Autom Conf (DAC)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2006.283899"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.136"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2006.1594713"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5\/4796865\/04796274.pdf?arnumber=4796274","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:00:41Z","timestamp":1633910441000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4796274\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,1]]},"references-count":47,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jproc.2008.2007471","relation":{},"ISSN":["0018-9219","1558-2256"],"issn-type":[{"value":"0018-9219","type":"print"},{"value":"1558-2256","type":"electronic"}],"subject":[],"published":{"date-parts":[[2009,1]]}}}