{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T20:50:55Z","timestamp":1773175855048,"version":"3.50.1"},"reference-count":114,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2009,1]]},"DOI":"10.1109\/jproc.2008.2007473","type":"journal-article","created":{"date-parts":[[2009,3,5]],"date-time":"2009-03-05T23:48:05Z","timestamp":1236296885000},"page":"123-140","source":"Crossref","is-referenced-by-count":107,"title":["Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits"],"prefix":"10.1109","volume":"97","author":[{"given":"Vasilis F.","family":"Pavlidis","sequence":"first","affiliation":[]},{"given":"Eby G.","family":"Friedman","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2004.834712"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1995.521445"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2006.1648629"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2004.1319401"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/IEMT.2004.1321633"},{"key":"ref30","article-title":"future ics go vertical","author":"garrou","year":"2005","journal-title":"Semiconductor Int"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.885073"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.883925"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.1995.517839"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.877252"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2006.1645834"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2005.1441289"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/96.659500"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2005.1554503"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.873612"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"562","DOI":"10.1145\/1278480.1278623","article-title":"interconnects in the third dimension: design challenges for 3d ics","author":"bernstein","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2006.1645676"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437621"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1109\/4.726547"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICEPT.2005.1564666"},{"key":"ref100","doi-asserted-by":"publisher","DOI":"10.1109\/5.929649"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2006.1645675"},{"key":"ref50","first-page":"681","article-title":"thermal analysis of heterogeneous 3-d ics with various integration scenarios","author":"chiang","year":"2001","journal-title":"Proc IEEE Int Electron Devices Meeting"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2002.805755"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2005.1554447"},{"key":"ref58","author":"goldberg","year":"1989","journal-title":"Genetic Algorithms in Search Optimization and Machine Learning"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378297"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2006.1594700"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1995.499244"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/92.609867"},{"key":"ref53","first-page":"277","article-title":"compact thermal model analysis for 3-d integrated circuits","author":"wilkerson","year":"2004","journal-title":"Proc Int Conf Mixed Design Integr Circuits Syst"},{"key":"ref52","first-page":"712","article-title":"cfd-micromesh: a fast geometrical modeling and mesh generation tool for 3d microsystem simulations","author":"tan","year":"2000","journal-title":"Proc Int Conf Model Simul Microsyst"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/EDL.1986.26341"},{"key":"ref4","first-page":"219","article-title":"stacked chip-to-chip interconnections using wafer bonding technology with dielectric bonding glues","author":"lu","year":"2001","journal-title":"Proc IEEE Int Interconnect Technol Conf"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/POLYTR.2001.973276"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609347"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2003.1216424"},{"key":"ref8","year":"2006","journal-title":"FDSOI Design Guide"},{"key":"ref49","first-page":"727","article-title":"full chip thermal analysis of planar (2-d) and vertically integrated (3-d) high performance ics","author":"im","year":"2000","journal-title":"Proc IEEE Int Electron Devices Meeting"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LECHPD.2002.1146728"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.882043"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/1057661.1057669"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2007.373897"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541535"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2006.1645677"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/16.711358"},{"key":"ref41","doi-asserted-by":"crossref","first-page":"352","DOI":"10.1109\/IEDM.1983.190514","article-title":"multilayer cmos device fabricated on laser recrystallized silicon islands","author":"akiyama","year":"1983","journal-title":"1983 International Electron Devices Meeting"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2005.1563724"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/EDL.1983.25766"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379062"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2004.824047"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127928"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1998.705245"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2000.855998"},{"key":"ref74","first-page":"409","article-title":"an innovative chip-to-wafer and wafer-to-wafer stacking","author":"lo","year":"2006","journal-title":"Proc IEEE Int Electron Compon Technol Conf"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.870069"},{"key":"ref78","doi-asserted-by":"crossref","first-page":"257","DOI":"10.1109\/SOC.2003.1241509","article-title":"3-d placement considering vertical interconnects","author":"kaya","year":"2003","journal-title":"Proc IEEE Int SOC Conf"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1145\/369691.369763"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585510"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.809651"},{"key":"ref61","first-page":"8","article-title":"corner block list: an effective and efficient topological representation of non-slicing floorplan","author":"hong","year":"2000","journal-title":"Proc IEEE\/ACM Int Conf Computer-Aided Design"},{"key":"ref63","first-page":"639","article-title":"the 3d-packing by meta data structure and packing heuristics","volume":"e83 a","author":"yamazaki","year":"2000","journal-title":"IEICE Trans Fundam Electron Commun Comput Sci"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466197"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.883857"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1145\/369691.369763"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329460"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2002.996687"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.885831"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1149\/1.1390894"},{"key":"ref109","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.842890"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.830932"},{"key":"ref108","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.22"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1993.393400"},{"key":"ref107","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560164"},{"key":"ref106","doi-asserted-by":"publisher","DOI":"10.1007\/b105353"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466143"},{"key":"ref105","first-page":"1005","article-title":"optimum tapered buffer","volume":"27","author":"punty","year":"1992","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774580"},{"key":"ref104","doi-asserted-by":"publisher","DOI":"10.1109\/4.58293"},{"key":"ref90","volume":"4","author":"ohtsuki","year":"1986","journal-title":"Advances in CAD for VLSI"},{"key":"ref103","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270271"},{"key":"ref102","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2001.912693"},{"key":"ref111","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2004.1261005"},{"key":"ref112","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1145\/1150019.1136497","article-title":"design and management of 3d chip multiprocessors using network-in-memory","author":"li","year":"2006","journal-title":"Proc Int Symp Comput Architect"},{"key":"ref110","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"ref98","first-page":"284","article-title":"yalmip: a toolbox for modeling and optimization in matlab","author":"lfberg","year":"2004","journal-title":"Proc IEEE Int Symp Computer-Aided Control Syst Design"},{"key":"ref99","year":"1995","journal-title":"Clock Distribution Networks in VLSI Circuits and Systems"},{"key":"ref96","year":"0","journal-title":"Metal User's Guide"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/92.974905"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.2001.954688"},{"key":"ref12","first-page":"233","article-title":"wire-length distribution of three-dimensional integrated circuits","author":"rahman","year":"1999","journal-title":"Proc IEEE Int Interconnect Technol Conf"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/92.902261"},{"key":"ref14","first-page":"99","article-title":"accurate interconnection lengths in three-dimensional computer systems","volume":"10","author":"stroobandt","year":"2000","journal-title":"IEICE Trans Inf Syst (Special Issue on Physical Design in Deep Submicron)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2002.1014915"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/16.915671"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/92.365457"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511666384"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.1257591"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/40.710867"},{"key":"ref83","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1145\/277044.277119","article-title":"Generic global placement and floorplanning","author":"eisenmann","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"ref114","author":"pavlidis","year":"2009","journal-title":"Three-Dimensional Integrated Circuit Design"},{"key":"ref113","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893649"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1145\/785411.785413"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.1145\/800158.805069"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"ref86","doi-asserted-by":"crossref","first-page":"132","DOI":"10.1145\/127601.127644","article-title":"Routing the 3-D chip","author":"enbody","year":"1991","journal-title":"28th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1109\/12.368006"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.860952"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5\/4796865\/04796277.pdf?arnumber=4796277","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:00:49Z","timestamp":1633910449000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4796277\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,1]]},"references-count":114,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jproc.2008.2007473","relation":{},"ISSN":["0018-9219"],"issn-type":[{"value":"0018-9219","type":"print"}],"subject":[],"published":{"date-parts":[[2009,1]]}}}