{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,1]],"date-time":"2026-03-01T02:38:03Z","timestamp":1772332683571,"version":"3.50.1"},"reference-count":48,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2009,1]]},"DOI":"10.1109\/jproc.2008.2007478","type":"journal-article","created":{"date-parts":[[2009,3,5]],"date-time":"2009-03-05T23:48:05Z","timestamp":1236296885000},"page":"161-174","source":"Crossref","is-referenced-by-count":27,"title":["3-D Data Storage, Power Delivery, and RF\/Optical Transceiver\u2014Case Studies of 3-D Integration From System Design Perspectives"],"prefix":"10.1109","volume":"97","author":[{"given":"Tong","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rino","family":"Micheloni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guoyan","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhaoran Rena","family":"Huang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James Jian-Qiang","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/22.798009"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2004.824837"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2007.382385"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2005.1441287"},{"key":"ref31","first-page":"19","article-title":"a wafer-level 3d ic technology platform","author":"gutmann","year":"2003","journal-title":"Proc Adv Metallization Conf"},{"key":"ref30","first-page":"386","author":"lu","year":"2005","journal-title":"Materials for Information Technology Devices Interconnects and Packaging"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332758"},{"key":"ref36","author":"razavi","year":"1998","journal-title":"RF Microelectronics"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493997"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1692568"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"219","DOI":"10.1109\/JSSC.2006.888299","article-title":"a 56-nm cmos 99- 8-gb multi-level nand flash memory with 10-mb\/s program throughput","volume":"42","author":"takeuchi","year":"2007","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/8.817654"},{"key":"ref11","author":"campardo","year":"2005","journal-title":"VLSI-Design of Non-Volatile Memories"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.841491"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1971.1054655"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511800467"},{"key":"ref15","author":"wicker","year":"1994","journal-title":"Reed-Solomon Codes and Their Applications"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885041"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2004.1319397"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/EPEP.2000.895497"},{"key":"ref19","author":"wu","year":"0","journal-title":"Delivering power integrity solutions for advanced IC packages"},{"key":"ref28","year":"0","journal-title":"Vertically packaged switched-mode power converter"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/APEX.2007.357505"},{"key":"ref27","year":"0","journal-title":"-axis processor power delivery system"},{"key":"ref3","article-title":"3d architecture for power delivery to microprocessors and asics","author":"lu","year":"2006","journal-title":"Proc 3rd Int Conf 3D Architect Semiconduct Integr Packag"},{"key":"ref6","article-title":"a 4 gb 2 b\/cell nand flash memory with embedded 5 b bch ecc for 36 mb\/s system read throughput","author":"micheloni","year":"2006","journal-title":"Proc Int Solid State Circuits Conf (ISSCC)"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1557\/PROC-1112-E02-01"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.818323"},{"key":"ref8","first-page":"290","article-title":"a 1.8 v 2 gb nand flash memory for mass storage applications","author":"lee","year":"2003","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.802355"},{"key":"ref2","first-page":"25","article-title":"3d integration: why, what, who, when?","author":"lu","year":"2007","journal-title":"Future Fab Int"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859027"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.873612"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1002\/0470014180"},{"key":"ref20","year":"0","journal-title":"The International Technology Roadmap for Semiconductors (ITRS)"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/22.846717"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1049\/el:20021047"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2006.306383"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/LEOS.2003.1251601"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/APEC.2006.1620599"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/8.660973"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2006.220793"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/8.244643"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2004.831897"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2004.825449"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2000.853162"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/8.817651"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"263","DOI":"10.1145\/1013235.1013302","article-title":"Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90nm Technology Generation","author":"schrom","year":"2004","journal-title":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design LPE"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5\/4796865\/04796877.pdf?arnumber=4796877","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:00:41Z","timestamp":1633910441000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4796877\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,1]]},"references-count":48,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jproc.2008.2007478","relation":{},"ISSN":["0018-9219"],"issn-type":[{"value":"0018-9219","type":"print"}],"subject":[],"published":{"date-parts":[[2009,1]]}}}