{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,7]],"date-time":"2026-07-07T00:44:08Z","timestamp":1783385048352,"version":"3.54.6"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2010,2,1]],"date-time":"2010-02-01T00:00:00Z","timestamp":1264982400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2010,2]]},"DOI":"10.1109\/jproc.2009.2034476","type":"journal-article","created":{"date-parts":[[2010,1,26]],"date-time":"2010-01-26T17:31:14Z","timestamp":1264527074000},"page":"333-342","source":"Crossref","is-referenced-by-count":88,"title":["FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics"],"prefix":"10.1109","volume":"98","author":[{"given":"S.A.","family":"Vitale","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"P.W.","family":"Wyatt","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"N.","family":"Checka","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"J.","family":"Kedzierski","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"C.L.","family":"Keast","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609524"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1088\/0268-1242\/23\/4\/045001"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/16.641359"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2006.74"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/16.387243"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/S0038-1101(02)00516-6"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.816915"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.1997.634912"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/S0038-1101(00)00107-6"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/VLSIT.1999.799322","article-title":"0.18 <ref_formula><tex notation=\"tex\">$\\mu{\\hbox{m}}$<\/tex><\/ref_formula> metal gate fully-depleted soi mosfets for advanced cmos application","author":"chen","year":"1999","journal-title":"1999 Symp VLSI Technol Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.1995.526478"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2006.885035"},{"key":"ref28","article-title":"workfunction-tuned tin metal gate fdsoi transistors for subthreshold operation","author":"vitale","year":"0","journal-title":"IEEE Trans Electron Devices"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2000.852617"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/16.772492"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.98"},{"key":"ref6","author":"gouker","year":"0","journal-title":"private communication"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2007.911974"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2008.4656272"},{"key":"ref8","author":"vittoz","year":"1994","journal-title":"Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9317(97)00173-1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2006.284409"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9317(99)00398-6"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2008.4656292"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1557\/PROC-0917-E12-02"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2006.1705253"},{"key":"ref21","first-page":"267","article-title":"fully-depleted soi technology using high-k and single-metal gate for 32 nm node lstp applications featuring 0.179 <ref_formula><tex notation=\"tex\">$\\mu \\hbox{m}^{2}$<\/tex><\/ref_formula> 6t-sram bitcell","author":"fenouillet-beranger","year":"2007","journal-title":"Tech Dig Int Electron Devices Meeting (IEDM)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469272"},{"key":"ref23","first-page":"61","article-title":"strained fdsoi cmos technology scalability down to 2.5 nm film thickness and 18 nm gate length with a <ref_formula><tex notation=\"tex\">$\\hbox{tin\/hfo}_{2}$<\/tex><\/ref_formula> gate stack","author":"barral","year":"2007","journal-title":"Tech Dig Int Electron Devices Meeting (IEDM)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469231"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346865"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5\/5395752\/05395759.pdf?arnumber=5395759","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:59:59Z","timestamp":1633913999000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5395759\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2]]},"references-count":31,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/jproc.2009.2034476","relation":{},"ISSN":["0018-9219","1558-2256"],"issn-type":[{"value":"0018-9219","type":"print"},{"value":"1558-2256","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,2]]}}}