{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T13:01:39Z","timestamp":1773406899356,"version":"3.50.1"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2010,2,1]],"date-time":"2010-02-01T00:00:00Z","timestamp":1264982400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2010,2]]},"DOI":"10.1109\/jproc.2009.2035453","type":"journal-article","created":{"date-parts":[[2010,1,26]],"date-time":"2010-01-26T17:31:14Z","timestamp":1264527074000},"page":"237-252","source":"Crossref","is-referenced-by-count":291,"title":["Ultralow-Power Design in Near-Threshold Region"],"prefix":"10.1109","volume":"98","author":[{"given":"D.","family":"Markovic","sequence":"first","affiliation":[]},{"given":"C.C.","family":"Wang","sequence":"additional","affiliation":[]},{"given":"L.P.","family":"Alarcon","sequence":"additional","affiliation":[]},{"family":"Tsung-Te Liu","sequence":"additional","affiliation":[]},{"given":"J.M.","family":"Rabaey","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5009039"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167511"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2002.146731"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839766"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705356"},{"key":"ref11","author":"sutherland","year":"1999","journal-title":"Logical Effort Designing Fast CMOS Circuits"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.52187"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.792617"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2007.136"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"883","DOI":"10.1109\/TVLSI.2008.2012054","article-title":"asynchronous computing in sense amplifier-based pass transistor logic","volume":"17","author":"liu","year":"2009","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2003.819206"},{"key":"ref17","author":"markovi","year":"2006","journal-title":"A power\/area optimal approach to VLSI signal processing"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892191"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996700"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839769"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.661211"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332730"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2002.146731"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831796"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1998.672471"},{"key":"ref5","first-page":"469","article-title":"optimization of <ref_formula><tex notation=\"tex\">${v}_{\\rm dd}$<\/tex><\/ref_formula> and <ref_formula><tex notation=\"tex\">${v}_{\\rm th}$<\/tex><\/ref_formula> for low-power and high-speed applications","author":"nose","year":"2000","journal-title":"Proc Asia South Pacific Design Automation Conf"},{"key":"ref8","author":"vittoz","year":"2005","journal-title":"Low-Power Electronics Design"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/BF01239381"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.604077"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852162"},{"key":"ref1","first-page":"211","article-title":"energy-delay tradeoffs in combinational logic using gate sizing and supply voltage optimization","author":"stojanovi","year":"2002","journal-title":"Proc Eur Solid-State Circuits Conf"},{"key":"ref20","first-page":"373","article-title":"a perturbation theory on statistical quantization effects in fixed-point dsp with non-stationary inputs","author":"shi","year":"2004","journal-title":"Proc Int Symp Circuits Syst"},{"key":"ref22","first-page":"196","article-title":"a 70 gops, 34 mw multi-carrier mimo chip in 3.5 <ref_formula><tex notation=\"tex\">${\\hbox{mm}}^{2}$ <\/tex><\/ref_formula>","author":"markovi","year":"2006","journal-title":"Proc Int Symp VLSI Circuits"},{"key":"ref21","author":"shi","year":"2004","journal-title":"Floating-point to fixed-point conversion"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839695"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1998.672474"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1998.672398"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1999.759238"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5\/5395752\/05395771.pdf?arnumber=5395771","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T01:00:39Z","timestamp":1633914039000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5395771\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,2]]},"references-count":33,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/jproc.2009.2035453","relation":{},"ISSN":["0018-9219","1558-2256"],"issn-type":[{"value":"0018-9219","type":"print"},{"value":"1558-2256","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,2]]}}}