{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:40:03Z","timestamp":1761324003518},"reference-count":59,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2015,3,1]],"date-time":"2015-03-01T00:00:00Z","timestamp":1425168000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"name":"DARPA\/CMO"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2015,3]]},"DOI":"10.1109\/jproc.2014.2387696","type":"journal-article","created":{"date-parts":[[2015,4,15]],"date-time":"2015-04-15T18:50:59Z","timestamp":1429123859000},"page":"355-378","source":"Crossref","is-referenced-by-count":23,"title":["Fundamental Underpinnings of Reconfigurable Computing Architectures"],"prefix":"10.1109","volume":"103","author":[{"given":"Andre","family":"DeHon","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1002\/spe.4380010203"},{"key":"ref38","first-page":"69","article-title":"Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)","author":"dehon","year":"0","journal-title":"Proc FPGA"},{"key":"ref33","first-page":"106","article-title":"Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes","author":"veredas","year":"0","journal-title":"Proc FPL"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/2.839324"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296444"},{"key":"ref30","first-page":"126","article-title":"Rapid—Reconfigurable pipelined datapath","author":"ebeling","year":"1996","journal-title":"Proc FPL"},{"key":"ref37","author":"hauck","year":"2008","journal-title":"Reconfigurable Computing The Theory and Practice of FPGA-Based Computation"},{"key":"ref36","article-title":"Tabula's time machine","author":"halfhill","year":"2010","journal-title":"Microprocessor Rep"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1997.624601"},{"key":"ref34","first-page":"115","article-title":"DPGA utilization and application","author":"dehon","year":"0","journal-title":"Proc FPGA"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/4.173120"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1985.6312192"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564808"},{"key":"ref2","first-page":"544","article-title":"On computable numbers, with an application to the entscheidungs problem: A correction","volume":"43","author":"turing","year":"0","journal-title":"Proc London Math Soc"},{"key":"ref1","article-title":"On computable numbers, with an application to the entscheidungs problem","volume":"42","author":"turing","year":"0","journal-title":"Proc London Math Soc"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296442"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/SFCS.1981.22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-68402-9_8"},{"key":"ref24","first-page":"97","article-title":"Architecture of centralized field-configurable memory","author":"wilton","year":"0","journal-title":"Proc FPGA"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/43.663827"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.834237"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.66"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1999.759296"},{"key":"ref51","first-page":"70","article-title":"Configurable computer solutions for automatic target recognition","author":"villasenor","year":"0","journal-title":"Proc IEEE FCCM"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145710"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718323"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068719"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2007.70235"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1995.477406"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/92.678870"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0433"},{"key":"ref52","first-page":"186","article-title":"Accelerating boolean satisfiability with configurable hardware","author":"zhong","year":"0","journal-title":"Proc IEEE FCCM"},{"key":"ref10","author":"leighton","year":"1992","journal-title":"Introduction to Parallel Algorithms and Architectures Arrays Trees Hypercubes"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1093\/oso\/9780195085914.001.0001","author":"greenlaw","year":"1995","journal-title":"Limits to Parallel Computation P-Completeness Theory"},{"key":"ref40","first-page":"33","article-title":"Organization of computer sytems: The fixed plus variable structure computer","author":"estrin","year":"0","journal-title":"Proc Western Joint Comput Conf"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2009.935263"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/0022-0000(84)90071-0"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/800135.804401"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084635"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"1901","DOI":"10.1109\/PROC.1966.5273","article-title":"very high-speed computing systems","volume":"54","author":"flynn","year":"1966","journal-title":"Proceedings of the IEEE"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2422.322412"},{"key":"ref19","article-title":"Randomized Routing on Fat-Trees, earlier MIT\/LCS\/TM-307","volume":"5","author":"greenberg","year":"1988","journal-title":"Randomness in Computation"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234194"},{"key":"ref3","first-page":"4","article-title":"Cramming more components onto integrated circuits","author":"moore","year":"1965","journal-title":"Electron Mag"},{"key":"ref6","doi-asserted-by":"crossref","DOI":"10.5479\/sil.538961.39088011475779","author":"von neumann","year":"1945","journal-title":"First Draft of a Report on the EDVAC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1984.1156607"},{"key":"ref8","first-page":"233","article-title":"A user programmable reconfigurable logic array","author":"carter","year":"0","journal-title":"Proc IEEE CICC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.2307\/2002620"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref9","first-page":"189","article-title":"Wordwidth, instructions, looping, virtualization—The role of sharing in absolute energy minimization","author":"dehon","year":"0","journal-title":"Proc FPGA"},{"key":"ref46","first-page":"7","article-title":"Scaling, power, the future of CMOS","author":"horowitz","year":"0","journal-title":"Proc IEDM"},{"key":"ref45","first-page":"365","article-title":"Dark silicon and the end of multicore scaling","author":"esmaeilzadeh","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"key":"ref48","author":"fuller","year":"2011","journal-title":"The Future of Computing Performance Game Over or Next Level?"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736044"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/2.839323"},{"key":"ref41","first-page":"172","article-title":"A high-performance microarchitecture with hardware-programmable functional units","author":"razdan","year":"0","journal-title":"Micro"},{"key":"ref44","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1109\/N-SSC.2007.4785534","article-title":"A 30 year retrospective on dennard's MOSFET scaling paper","volume":"12","author":"bohr","year":"0","journal-title":"IEEE Solid-State Circuits Society Newsletter"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5\/7086369\/07086421.pdf?arnumber=7086421","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,5]],"date-time":"2022-05-05T04:22:39Z","timestamp":1651724559000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7086421\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3]]},"references-count":59,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/jproc.2014.2387696","relation":{},"ISSN":["0018-9219","1558-2256"],"issn-type":[{"value":"0018-9219","type":"print"},{"value":"1558-2256","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,3]]}}}