{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T09:31:01Z","timestamp":1782984661573,"version":"3.54.5"},"reference-count":76,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2015,8,1]],"date-time":"2015-08-01T00:00:00Z","timestamp":1438387200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2015,8]]},"DOI":"10.1109\/jproc.2015.2435018","type":"journal-article","created":{"date-parts":[[2015,7,7]],"date-time":"2015-07-07T18:27:15Z","timestamp":1436293635000},"page":"1331-1345","source":"Crossref","is-referenced-by-count":50,"title":["Evolution of Memory Architecture"],"prefix":"10.1109","volume":"103","author":[{"given":"Ravi","family":"Nair","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref73","author":"hawkins","year":"2006","journal-title":"Hierarchical temporal memory Concepts theory and terminology"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.48"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/101.8118"},{"key":"ref70","author":"hillis","year":"1989","journal-title":"The Connection Machine"},{"key":"ref76","doi-asserted-by":"crossref","first-page":"668","DOI":"10.1126\/science.1254642","article-title":"A million spiking-neuron integrated circuit with a scalable communication network and interface","volume":"345","author":"merolla","year":"2014","journal-title":"Science"},{"key":"ref74","year":"0","journal-title":"The path to machine intelligence"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/2095536.2095583"},{"key":"ref75","year":"0","journal-title":"The SyNAPSE program"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629577"},{"key":"ref33","doi-asserted-by":"crossref","DOI":"10.1145\/343477.343502","article-title":"Towards robust distributed systems","author":"brewer","year":"0","journal-title":"ACM Symp Principles Distrib Computing"},{"key":"ref32","author":"skjellum","year":"1999","journal-title":"Using MPI Portable Parallel Programming with the Message Passing Interface"},{"key":"ref31","year":"2011","journal-title":"The blue gene\/Q compute chip"},{"key":"ref30","year":"0","journal-title":"TOP 500 Supercomputer Sites"},{"key":"ref37","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1713254.1713276","article-title":"The case for RAMClouds: Scalable high-performance storage entirely in DRAM","volume":"43","author":"ousterhout","year":"2010","journal-title":"SIGOPS Oper Syst Rev"},{"key":"ref36","first-page":"28","article-title":"The SAP HANA database&#x2014;An architecture overview","volume":"35","author":"f\u00e4rber","year":"2012","journal-title":"IEEE Data Eng Bull"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1394127.1394128"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2012.37"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2004.29"},{"key":"ref62","year":"0","journal-title":"Information Society"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1126\/science.1200970"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540712"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/289.291"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006439"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917757"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1147\/rd.494.0589"},{"key":"ref29","author":"culler","year":"1997","journal-title":"Parallel Computer Architecture A Hardware\/Software Approach"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2014.8"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/2.74"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"126","DOI":"10.1145\/641675.642111","article-title":"A preliminary architecture for a basic data-flow processor","volume":"3","author":"dennis","year":"1975","journal-title":"ACM SIGARCH Comput Architect News"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/85.238389"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508271"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MSST.2011.5937225"},{"key":"ref21","year":"0","journal-title":"Wear leveling in micron NAND memory"},{"key":"ref24","article-title":"NAND-flash: Fast storage or slow memory?","author":"sudan","year":"0","journal-title":"Proc Non-Volatile Memory Workshop"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2007.57"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"ref25","first-page":"14","article-title":"Operating system support for NVM+DRAM hybrid main memory","author":"mogul","year":"0","journal-title":"Proc 12th Conf Hot Topics Oper Syst"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1994.108"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514197"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2015.2409732"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600213"},{"key":"ref57","first-page":"190","article-title":"ND: Analyzing the impact of 3D-stacked memory+logic devices on map reduce workloads","author":"pugsley","year":"0","journal-title":"Proc Int Symp Perform Anal Syst Softw"},{"key":"ref56","author":"pawlowski","year":"2011","journal-title":"Hybrid Memory Cube Breakthrough DRAM Performance with A Fundamentally Re-architected DRAM Subsystem"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007462"},{"key":"ref54","article-title":"The POWER8 processor: Designed for big data, analytics, cloud environments","author":"friedrich","year":"0","journal-title":"Proc IEEE Int Conf IC Design Technol"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744334"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/2.612252"},{"key":"ref10","year":"1980","journal-title":"Circuits and systems product guide"},{"key":"ref11","author":"jacob","year":"2007","journal-title":"Memory System Cache DRAM Disk"},{"key":"ref40","author":"sanfilippo","year":"0","journal-title":"Redis"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/356571.356573"},{"key":"ref13","year":"0","journal-title":"Under the hood Of POWER7 processor caches"},{"key":"ref14","year":"0","journal-title":"IBM power system E880 data sheet"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908006"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1504\/IJHPSA.2012.050990"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/16.278509"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1978.1051122"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118382"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/6.591665"},{"key":"ref6","year":"0","journal-title":"Magnetic drum data processing machine announcement"},{"key":"ref5","year":"0","journal-title":"Electronic computers within the Ordnance Corps chapter III&#x2014;EDVAC"},{"key":"ref8","year":"0","journal-title":"The CDC 6600 arrives at CERN"},{"key":"ref7","year":"0","journal-title":"Magnetic-core memory"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/2.375174"},{"key":"ref9","article-title":"Field-effect transistor memory","author":"dennard","year":"1968"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2013.46"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/2517349.2522724"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2014.55"},{"key":"ref42","year":"0","journal-title":"Ibm Netezza Data Warehouse Appliances"},{"key":"ref41","first-page":"72","article-title":"Distributed caching with memcached","volume":"2004","author":"fitzpatrick","year":"2004","journal-title":"Linux J"},{"key":"ref44","article-title":"Near-data computation: It's not (just) about performance","author":"swanson","year":"0","journal-title":"First Workshop Near Data Process"},{"key":"ref43","article-title":"The Netezza data appliance architecture: A platform for high performance data warehousing and analytics","author":"francisco","year":"2011","journal-title":"IBM Redbooks"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5\/7158995\/07151782.pdf?arnumber=7151782","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,12]],"date-time":"2023-08-12T03:04:58Z","timestamp":1691809498000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7151782\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,8]]},"references-count":76,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/jproc.2015.2435018","relation":{},"ISSN":["0018-9219","1558-2256"],"issn-type":[{"value":"0018-9219","type":"print"},{"value":"1558-2256","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,8]]}}}