{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,24]],"date-time":"2026-01-24T14:42:50Z","timestamp":1769265770522,"version":"3.49.0"},"reference-count":223,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2015,11,1]],"date-time":"2015-11-01T00:00:00Z","timestamp":1446336000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000001","name":"U.S. National Science Foundation","doi-asserted-by":"publisher","award":["1162087"],"award-info":[{"award-number":["1162087"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","award":["2264"],"award-info":[{"award-number":["2264"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Mentor Graphics Corporation"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/jproc.2015.2478963","type":"journal-article","created":{"date-parts":[[2015,10,9]],"date-time":"2015-10-09T18:36:38Z","timestamp":1444415798000},"page":"1985-2003","source":"Crossref","is-referenced-by-count":70,"title":["Progress and Challenges in VLSI Placement Research"],"prefix":"10.1109","volume":"103","author":[{"given":"Igor L.","family":"Markov","sequence":"first","affiliation":[]},{"given":"Jin","family":"Hu","sequence":"additional","affiliation":[]},{"given":"Myung-Chul","family":"Kim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref170","first-page":"142","article-title":"Analytical power\/timing optimization technique for digital systems","author":"ruehli","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref172","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643590"},{"key":"ref171","doi-asserted-by":"publisher","DOI":"10.1109\/CEC.2002.1006263"},{"key":"ref174","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.858273"},{"key":"ref173","author":"sarrafzadeh","year":"2002","journal-title":"Modern Placement Techniques"},{"key":"ref176","doi-asserted-by":"publisher","DOI":"10.1145\/1353629.1353668"},{"key":"ref175","doi-asserted-by":"publisher","DOI":"10.1145\/639929.639941"},{"key":"ref178","doi-asserted-by":"publisher","DOI":"10.1145\/127601.127707"},{"key":"ref177","first-page":"162","article-title":"Monotone operators in Banach space and nonlinear partial differential equations","author":"showalter","year":"1997","journal-title":"Math Surveys Monogr"},{"key":"ref168","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055184"},{"key":"ref169","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687467"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923063"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.927760"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382637"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654155"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687454"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjtsldm.2.145"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006148"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391651"},{"key":"ref35","first-page":"218","article-title":"Constraint graph-based macro placement for modern mixed-size circuit designs","author":"chen","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776034"},{"key":"ref181","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.925783"},{"key":"ref180","doi-asserted-by":"publisher","DOI":"10.1145\/1353629.1353640"},{"key":"ref185","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114836"},{"key":"ref184","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.927758"},{"key":"ref183","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217531"},{"key":"ref182","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185188"},{"key":"ref189","first-page":"212","article-title":"Guiding global placement with wire density","author":"tsota","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref188","doi-asserted-by":"publisher","DOI":"10.1145\/127601.122882"},{"key":"ref187","first-page":"318","article-title":"Proud: A fast sea-of-gates placement algorithm","author":"tsay","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref186","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.1261846"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/505388.505425"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-68739-1_10"},{"key":"ref179","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364463"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1119772.1119835"},{"key":"ref20","first-page":"124","article-title":"Timing influenced layout design","author":"burstein","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/43.784119"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2723572"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/43.892854"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337549"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055177"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1929943.1929950"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105310"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654234"},{"key":"ref154","doi-asserted-by":"crossref","first-page":"275","DOI":"10.1145\/277044.277121","article-title":"Congestion driven quadratic placement","author":"parakh","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"ref153","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.41"},{"key":"ref156","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593120"},{"key":"ref155","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006156"},{"key":"ref150","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653647"},{"key":"ref152","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006155"},{"key":"ref151","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.76"},{"key":"ref146","author":"orshansky","year":"2010","journal-title":"Design for Manufacturability and Statistical Design A Constructive Approach (Integrated Circuits and Systems)"},{"key":"ref147","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160950"},{"key":"ref148","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320159"},{"key":"ref149","first-page":"48","article-title":"An efficient and effective detailed placement algorithm","author":"pan","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref59","first-page":"91","article-title":"DOMINO: Deterministic placement improvement with hill-climbing capabilities","author":"doll","year":"0","journal-title":"Very Large Scale Integration (VLSI)"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/43.317462"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687466"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560058"},{"key":"ref55","first-page":"188","article-title":"A robust detailed placement for mixed-size IC designs","author":"cong","year":"0","journal-title":"Proc Asia South Pacific Design Autom Conf"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059886"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006158"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160952"},{"key":"ref40","first-page":"650","article-title":"RISA: Accurate and efficient placement routability modeling","author":"cheng","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref167","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.09.003"},{"key":"ref166","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907271"},{"key":"ref165","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.888260"},{"key":"ref164","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855969"},{"key":"ref163","doi-asserted-by":"crossref","first-page":"711","DOI":"10.1109\/TCAD.2005.846367","article-title":"Sensitivity guided net weighting for placement driven synthesis","volume":"24","author":"ren","year":"2005","journal-title":"IEEE Trans Comput -Aided Design"},{"key":"ref162","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357976"},{"key":"ref161","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065712"},{"key":"ref160","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1995.521529"},{"key":"ref4","first-page":"307","article-title":"Fractional cut: Improved recursive bisection placement","author":"agnihorti","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2005.08.003"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055179"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/640000.640035"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1735023.1735028"},{"key":"ref159","doi-asserted-by":"publisher","DOI":"10.1145\/640015.640016"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.890096"},{"key":"ref49","first-page":"59","article-title":"IPR: An integrated placement and routing algorithm","author":"chu","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref157","first-page":"285","article-title":"Keeping hot chips cool","author":"puri","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429442"},{"key":"ref158","first-page":"788","article-title":"Pushing ASIC performance in a power envelope","author":"puri","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228498"},{"key":"ref45","first-page":"1104","article-title":"Hierarchical global floor placement using simulated annealing and network flow area migration","author":"choi","year":"0","journal-title":"Proc Design Autom Test Eur Conf Exhibit"},{"key":"ref48","first-page":"801","article-title":"How accurately can we model timing in a placement engine","author":"chowdhary","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/2560519.2560523"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065791"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1984.1270078"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837347"},{"key":"ref43","first-page":"1470","article-title":"Register placement for high-performance circuits","author":"chiang","year":"0","journal-title":"Proc Design Autom Test Eur Conf Exhibit"},{"key":"ref73","article-title":"Method and system for high speed detailed placement of cells within an integrated circuit design","author":"hill","year":"2001"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488922"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105308"},{"key":"ref70","first-page":"88","article-title":"Circuit placement for predictable performance","author":"hauge","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654240"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024875"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-28566-0_12"},{"key":"ref75","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370560"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105309"},{"key":"ref79","first-page":"739","article-title":"Congestion minimization during placement without estimation","author":"hu","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2000.840038"},{"key":"ref62","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1145\/277044.277119","article-title":"Generic global placement and floorplanning","author":"eisenmann","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"ref61","first-page":"133","article-title":"Chip layout optimization using critical path weighting","author":"dunlop","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref63","first-page":"175","article-title":"A linear-time heuristic for improving network partitions","author":"fiduccia","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1992.227845"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.873901"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1145\/330855.331040"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.156242"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/IWSOC.2003.1212999"},{"key":"ref69","doi-asserted-by":"crossref","first-page":"531","DOI":"10.1145\/157485.165015","article-title":"prime: a timing-driven placement tool using a piecewise linear resistive network approach","author":"hamada","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"ref197","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357975"},{"key":"ref198","first-page":"268","article-title":"Efficient timing closure without timing driven placement and routing","author":"vujkovic","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref199","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717776"},{"key":"ref193","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228500"},{"key":"ref194","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429456"},{"key":"ref195","first-page":"453","article-title":"RQL: Global placement via relaxed quadratic spreading and linearization","author":"viswanathan","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref196","doi-asserted-by":"publisher","DOI":"10.1145\/1735023.1735048"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9591-6"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1145\/2591513.2591540"},{"key":"ref190","doi-asserted-by":"publisher","DOI":"10.1109\/EURDAC.1993.410619"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1145\/332357.332401"},{"key":"ref191","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112223"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2177459"},{"key":"ref192","doi-asserted-by":"publisher","DOI":"10.1145\/1960397.1960429"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391513"},{"key":"ref90","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.883918"},{"key":"ref98","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1999.760005"},{"key":"ref99","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123057"},{"key":"ref96","doi-asserted-by":"publisher","DOI":"10.1145\/988952.989004"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1145\/1455229.1455245"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2004.1349331"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429428"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488920"},{"key":"ref83","first-page":"35","article-title":"Completing high-quality routes","author":"hu","year":"0","journal-title":"Proc Int Symp Phys Design"},{"key":"ref80","doi-asserted-by":"crossref","first-page":"1188","DOI":"10.1109\/TCAD.2005.850802","article-title":"Multilevel fixed-point-addition-based VLSI placement","volume":"24","author":"hu","year":"2005","journal-title":"IEEE Trans Comput -Aided Design"},{"key":"ref89","first-page":"370","article-title":"Performance-driven placement of cell based ICs","author":"jackson","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref85","article-title":"Multiterminal flows in a hypergraph","author":"hu","year":"1985","journal-title":"VLSI Circuit Layout Theory and Design"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775888"},{"key":"ref87","first-page":"165","article-title":"Mongrel: Hybrid techniques for standard cell placement","author":"hur","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref88","year":"0","journal-title":"International Technology Roadmap for Semiconductors (ITRS)"},{"key":"ref200","first-page":"145","article-title":"On the behaviour of congestion minimization during placement","author":"wang","year":"0","journal-title":"Proc Int Symp Phys Design"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2014.7004188"},{"key":"ref100","first-page":"343","article-title":"Multilevel k-way hypergraph partitioning","author":"karypis","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref209","doi-asserted-by":"publisher","DOI":"10.1145\/981066.981110"},{"key":"ref203","first-page":"147","article-title":"Multicenter congestion estimation and minimization during placement","author":"wang","year":"0","journal-title":"Proc Int Symp Phys Design"},{"key":"ref204","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378498"},{"key":"ref201","first-page":"185","article-title":"Model and minimization of routing congestion","author":"wang","year":"0","journal-title":"Proc Asia South Pacific Design Autom Conf"},{"key":"ref202","doi-asserted-by":"publisher","DOI":"10.1109\/43.875296"},{"key":"ref207","article-title":"Hard macros will revolutionize SoC design","author":"wein","year":"2004","journal-title":"EE Times"},{"key":"ref208","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397320"},{"key":"ref205","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228497"},{"key":"ref206","author":"wang","year":"2009","journal-title":"Electronic Design Automation Synthesis Verification and Test"},{"key":"ref211","author":"wong","year":"2009","journal-title":"Nano-CMOS Design for Manufacturability"},{"key":"ref210","doi-asserted-by":"publisher","DOI":"10.1145\/1053355.1053377"},{"key":"ref212","doi-asserted-by":"publisher","DOI":"10.1145\/1735023.1735046"},{"key":"ref213","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065732"},{"key":"ref214","first-page":"576","article-title":"FastRoute 4.0: Global router with efficient via minimization","author":"xu","year":"0","journal-title":"Proc Asia South Pacific Design Autom Conf"},{"key":"ref215","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2114950"},{"key":"ref216","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630028"},{"key":"ref217","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.809660"},{"key":"ref218","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.781232"},{"key":"ref219","first-page":"24","article-title":"Timing constraints for correct peformance","author":"youssef","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref220","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2401571"},{"key":"ref222","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687465"},{"key":"ref221","first-page":"161","article-title":"ISPD 2014 benchmarks with sub-45 nm technology rules for detailed-routing-driven placement","author":"yutsis","year":"0","journal-title":"Proc Int Symp Phys Design"},{"key":"ref223","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012741"},{"key":"ref127","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593181"},{"key":"ref126","first-page":"626","article-title":"A fast physical constraint generator for timing driven placement","author":"luk","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref125","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593133"},{"key":"ref124","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118437"},{"key":"ref129","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488923"},{"key":"ref128","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837324"},{"key":"ref130","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147190"},{"key":"ref133","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065628"},{"key":"ref134","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"ref131","first-page":"346","article-title":"DPlace2.0: A stable and efficient analytical placement based on diffusion","author":"luo","year":"0","journal-title":"Proc Asia South Pacific Design Autom Conf"},{"key":"ref132","first-page":"41","article-title":"Computational geometry based placement migration","author":"luo","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref136","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681611"},{"key":"ref135","doi-asserted-by":"publisher","DOI":"10.1145\/640000.640042"},{"key":"ref138","first-page":"322","article-title":"A timing-driven macro-cell placement algorithm","author":"mo","year":"0","journal-title":"Proc Int Conf Comput Design"},{"key":"ref137","first-page":"177","article-title":"A force-directed macro-cell placer","author":"mo","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref139","doi-asserted-by":"publisher","DOI":"10.1145\/1391962.1391975"},{"key":"ref140","doi-asserted-by":"publisher","DOI":"10.1109\/43.31546"},{"key":"ref141","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-68739-1"},{"key":"ref142","article-title":"Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer","author":"naylor","year":"2001"},{"key":"ref143","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2004.1337555"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1044111.1044116"},{"key":"ref144","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055190"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825852"},{"key":"ref145","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9260(99)00022-X"},{"key":"ref109","first-page":"361","article-title":"ICCAD-2014 CAD contest in incremental timing-driven placement and benchmark suite","author":"kim","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref108","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691130"},{"key":"ref107","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160958"},{"key":"ref106","first-page":"747","article-title":"ComPLx: A competitive primal-dual Lagrange optimization for global placement","author":"kim","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref105","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2170567"},{"key":"ref104","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105307"},{"key":"ref103","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654229"},{"key":"ref102","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2174640"},{"key":"ref111","first-page":"172","article-title":"A novel net weighting algorithm for timing-driven placement","author":"kong","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref112","first-page":"108","article-title":"Tripple patterning lithography aware optimization for standard cell based design","author":"kuang","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref110","doi-asserted-by":"publisher","DOI":"10.1109\/43.67789"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1201\/9781420013481"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"213","DOI":"10.1007\/3-540-63465-7_226","article-title":"VPR: A new packing, placement and routing tool for FPGA research","volume":"1304","author":"betz","year":"1997","journal-title":"Field-Programmable Logic and Applications"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176579"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/505388.505391"},{"key":"ref14","first-page":"117","article-title":"Faster optimal single-row placement with fixed ordering","author":"brenner","year":"0","journal-title":"Proc Design Autom Test Eur Conf Exhibit"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.836733"},{"key":"ref16","first-page":"591","article-title":"Faster and better global placement by a new transportation algorithm","author":"brenner","year":"0","journal-title":"Proc Design Autom Conf"},{"key":"ref118","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466187"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.927674"},{"key":"ref117","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.133"},{"key":"ref18","first-page":"343","article-title":"Min-cut placement","volume":"10","author":"breuer","year":"1977","journal-title":"J Design Aut and Fault-tolerant Computing"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008293323270"},{"key":"ref119","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382607"},{"key":"ref114","author":"lavagno","year":"2006","journal-title":"EDA for IC Implementation Circuit Design Process Technology"},{"key":"ref113","first-page":"195","article-title":"Managing power and performance for system-on-chip designs using voltage islands","author":"lackey","year":"0","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref116","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419819"},{"key":"ref115","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2173490"},{"key":"ref120","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160936"},{"key":"ref121","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466121"},{"key":"ref122","doi-asserted-by":"publisher","DOI":"10.1145\/1119772.1119934"},{"key":"ref123","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593181"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5\/7302610\/07295553.pdf?arnumber=7295553","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T15:58:42Z","timestamp":1642003122000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7295553\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":223,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jproc.2015.2478963","relation":{},"ISSN":["0018-9219","1558-2256"],"issn-type":[{"value":"0018-9219","type":"print"},{"value":"1558-2256","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,11]]}}}