{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,18]],"date-time":"2026-08-18T15:23:50Z","timestamp":1787066630978,"version":"3.56.0"},"reference-count":202,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/jproc.2017.2665781","type":"journal-article","created":{"date-parts":[[2017,3,28]],"date-time":"2017-03-28T19:21:13Z","timestamp":1490728873000},"page":"1609-1633","source":"Crossref","is-referenced-by-count":259,"title":["Reviewing the Evolution of the NAND Flash Technology"],"prefix":"10.1109","volume":"105","author":[{"given":"Christian","family":"Monzio Compagnoni","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Akira","family":"Goda","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alessandro S.","family":"Spinelli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Peter","family":"Feeley","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrea L.","family":"Lacaita","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Angelo","family":"Visconti","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref170","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2001.979396"},{"key":"ref172","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346903"},{"key":"ref171","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346902"},{"key":"ref174","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418970"},{"key":"ref173","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2007.4339708"},{"key":"ref176","first-page":"136","article-title":"Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices","author":"katsumata","year":"2009","journal-title":"Symp VLSI Technol Dig"},{"key":"ref175","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424261"},{"key":"ref178","first-page":"668","article-title":"Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application","author":"whang","year":"2010","journal-title":"IEDM Tech Dig"},{"key":"ref177","first-page":"192","article-title":"Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory","author":"jang","year":"2009","journal-title":"Symp VLSI Technol Dig"},{"key":"ref168","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917559"},{"key":"ref169","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-012-0716-0"},{"key":"ref39","first-page":"422","article-title":"A 19 nm 112.8 mm $^{2}~64$ Gb multi-level flash memory with 400 Mb\/s\/pin 1.8 V toggle mode interface","author":"shibata","year":"2012","journal-title":"Proc ISSCC"},{"key":"ref38","first-page":"436","article-title":"128 Gb 3b\/cell NAND flash memory in 19 nm technology with 18 MB\/s write rate and 400 Mb\/s toggle mode","author":"li","year":"2012","journal-title":"Proc ISSCC"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/4.328638"},{"key":"ref32","first-page":"424","article-title":"A 45 nm self-aligned-contact process 1 Gb NOR flash with 5 MB\/s program speed","author":"javanifard","year":"2008","journal-title":"Proc ISSCC"},{"key":"ref31","first-page":"476","article-title":"A 65 nm 1 Gb 2 b\/cell NOR flash with 2.25 MB\/s program throughput and 400 MB\/s DDR interface","author":"villa","year":"2007","journal-title":"Proc ISSCC"},{"key":"ref30","first-page":"52","article-title":"A 125 MHz burst-mode flexible read-while-write 256 Mbit 2b\/c 1.8V NOR flash memory","author":"villa","year":"2005","journal-title":"Proc ISSCC"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007152"},{"key":"ref36","first-page":"420","article-title":"A 34 MB\/s-program-throughput 16 Gb MLC NAND with all-bitline architecture in 56 nm","author":"cernea","year":"2008","journal-title":"Proc ISSCC"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542301"},{"key":"ref34","first-page":"128","article-title":"A low-power 64Gb MLC NAND-flash memory in 15 nm CMOS technology","author":"sako","year":"2015","journal-title":"Proc ISSCC"},{"key":"ref181","first-page":"188","article-title":"Multi-layered vertical gate NAND flash overcoming stacking limit for terabit density storage","author":"kim","year":"2009","journal-title":"Symp VLSI Technol Dig"},{"key":"ref180","first-page":"142","article-title":"A 768 Gb 3b\/cell 3D-floating-gate NAND flash memory","author":"tanaka","year":"2016","journal-title":"Proc ISSCC"},{"key":"ref185","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2012.6466681"},{"key":"ref184","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6478963"},{"key":"ref183","first-page":"68","article-title":"A highly scalable vertical gate (VG) 3D NAND flash with robust program disturb immunity using a novel PN diode decoding structure","author":"hung","year":"2011","journal-title":"Symp VLSI Technol Dig"},{"key":"ref182","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2010.5556199"},{"key":"ref189","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2318716"},{"key":"ref188","doi-asserted-by":"publisher","DOI":"10.1533\/9780857098092.1.27"},{"key":"ref187","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2352293"},{"key":"ref186","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242476"},{"key":"ref28","first-page":"236","article-title":"A 172 mm $^{2}~32$ Gb MLC NAND flash memory in 34 nm CMOS","author":"zeng","year":"2009","journal-title":"Proc ISSCC"},{"key":"ref27","first-page":"1","article-title":"A 4Gb 2b\/cell NAND flash memory with embedded 5b BCH ECC for 36 MB\/s system read throughput","author":"micheloni","year":"2006","journal-title":"Proc ISSCC"},{"key":"ref179","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479011"},{"key":"ref29","first-page":"54","article-title":"A 90 nm 512 Mb 166 MHz multilevel cell flash memory with 1.5 MByte\/s programming","author":"taub","year":"2005","journal-title":"Proc ISSCC"},{"key":"ref20","first-page":"1","article-title":"A 56 nm CMOS 99 mm $^{2}~8$ Gb multi-level NAND flash memory with 10 MB\/s program throughput","author":"takeuchi","year":"2006","journal-title":"Proc ISSCC"},{"key":"ref22","first-page":"442","article-title":"A 159 mm $^{2}~32$ nm 32 Gb MLC NAND-flash memory with 200 MB\/s asynchronous DDR interface","author":"kim","year":"2010","journal-title":"Proc ISSCC"},{"key":"ref21","first-page":"426","article-title":"A 50 nm 8Gb NAND flash memory with 100 MB\/s program throughput and 200 MB\/s DDR interface","author":"nobunaga","year":"2008","journal-title":"Proc ISSCC"},{"key":"ref24","first-page":"198","article-title":"A 151 mm $^{2}~64$ Gb MLC NAND flash memory in 24 nm CMOS technology","author":"fukuda","year":"2011","journal-title":"Proc ISSCC"},{"key":"ref23","first-page":"212","article-title":"A 7MB\/s 64 Gb 3-bit\/cell DDR NAND flash memory in 20 nm-node technology","author":"park","year":"2011","journal-title":"Proc ISSCC"},{"key":"ref26","first-page":"1","article-title":"Inherent issues and challenges of program disturbance of 3D NAND flash cell","author":"shim","year":"2012","journal-title":"Proc IMW"},{"key":"ref25","first-page":"1","article-title":"25 nm 64 Gb 130 mm2 3 bpc NAND flash memory","author":"goldman","year":"2011","journal-title":"Proc IMW"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1992.229256"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.2003332"},{"key":"ref154","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2150751"},{"key":"ref153","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2010.5488762"},{"key":"ref156","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2014.6860600"},{"key":"ref155","first-page":"2a.1.1","article-title":"Assessment of distributed-cycling schemes on 45nm NOR flash memory arrays","author":"miccoli","year":"2012","journal-title":"Proc IRPS"},{"key":"ref150","first-page":"497","article-title":"Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90 nm NAND flash memory cells","author":"lee","year":"2003","journal-title":"Proc IRPS"},{"key":"ref152","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2006.251188"},{"key":"ref151","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2004.824360"},{"key":"ref146","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.09.002"},{"key":"ref147","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2009.2026658"},{"key":"ref148","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2000.843915"},{"key":"ref149","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2001.934976"},{"key":"ref59","first-page":"44","article-title":"A 146 mm $^{2}~8$ Gb NAND flash memory with 70 nm CMOS technology","author":"hara","year":"2005","journal-title":"Proc ISSCC"},{"key":"ref58","first-page":"1","article-title":"A 3.3 V 4 Gb four-level NAND flash memory with 90 nm CMOS technology","author":"lee","year":"2004","journal-title":"Proc ISSCC"},{"key":"ref57","first-page":"1","article-title":"A 3.3 V 1 Gb multi-level NAND flash memory with non-uniform threshold voltage distribution","author":"cho","year":"2001","journal-title":"Proc ISSCC"},{"key":"ref56","first-page":"1","article-title":"A 1.8 V 1 Gb NAND flash memory with 0.12 $\\mu \\text{m}$ STI process technology","author":"lee","year":"2002","journal-title":"Proc ISSCC"},{"key":"ref55","first-page":"112","article-title":"A 130 mm2 256 Mb NAND flash with shallow trench isolation technology","author":"imamiya","year":"1999","journal-title":"Proc ISSCC"},{"key":"ref54","first-page":"128","article-title":"A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme","author":"suh","year":"1995","journal-title":"Proc ISSCC"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.2013.6552766"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.2003230"},{"key":"ref40","first-page":"430","article-title":"A 64 Gb 533 Mb\/s DDR interface MLC NAND flash in sub-20 nm technology","author":"lee","year":"2012","journal-title":"Proc ISSCC"},{"key":"ref167","first-page":"1","article-title":"Scaling challenges in NAND flash device toward 10 nm technology","author":"lee","year":"2012","journal-title":"Proc IMW"},{"key":"ref166","doi-asserted-by":"publisher","DOI":"10.1109\/NVSMW.2007.4290578"},{"key":"ref165","first-page":"36","article-title":"The air spacer technology for improving the cell distribution in 1 giga bit NAND flash memory","author":"kang","year":"2006","journal-title":"Proc Non-Volatile Semiconductor Memory Workshop"},{"key":"ref164","first-page":"970","article-title":"Variability effects on the $V_{T}$ distribution of nanoscale NAND flash memories","author":"spessot","year":"2010","journal-title":"Proc IRPS"},{"key":"ref163","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2008.2009555"},{"key":"ref162","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2005.10.014"},{"key":"ref161","doi-asserted-by":"crossref","first-page":"264","DOI":"10.1109\/55.998871","article-title":"Effects of floating-gate interference on NAND flash memory cell operation","volume":"23","author":"lee","year":"2002","journal-title":"IEEE Electron Device Lett"},{"key":"ref160","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2008.2000964"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409618"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062960"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2604297"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"204","DOI":"10.1109\/JSSC.2015.2474117","article-title":"A 128 Gb 3b\/cell V-NAND flash memory with 1 Gb\/s I\/O rate","volume":"51","author":"jeong","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref8","first-page":"61","article-title":"A $0.67~\\mu \\text{m}^{2}$ self-aligned shallow trench isolation cell (SA-STI cell) for 3 V-only 256 Mbit NAND EEPROMs","author":"aritome","year":"1994","journal-title":"IEDM Tech Dig"},{"key":"ref159","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2617890"},{"key":"ref7","first-page":"430","article-title":"A 120 mm $^{2}~16$ Gb 4-MLC NAND flash memory with 43 nm CMOS technology","author":"kanda","year":"2008","journal-title":"Proc ISSCC"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.1995.520891"},{"key":"ref157","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2016.7574569"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2013.01.006"},{"key":"ref158","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2617888"},{"key":"ref46","first-page":"158","article-title":"Reliability performance of ETOX based flash memories","author":"verma","year":"1988","journal-title":"Proc IRPS"},{"key":"ref45","first-page":"464","article-title":"A new flash $\\text{E}^{2}$ PROM cell using triple polysilicon technology","author":"masuoka","year":"1984","journal-title":"IEDM Tech Dig"},{"key":"ref48","doi-asserted-by":"crossref","first-page":"1149","DOI":"10.1109\/4.475701","article-title":"A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme","volume":"30","author":"suh","year":"1995","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1990.237214"},{"key":"ref42","first-page":"103","article-title":"A $2.3~\\mu \\text{m}^{2}$ memory cell structure for 16 Mb NAND EEPROMs","author":"shirota","year":"1990","journal-title":"IEDM Tech Dig"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.1990.111042"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2013.2278083"},{"key":"ref43","first-page":"105","article-title":"A 4-Mbit NAND-EEPROM with tight programmed $\\text{V}\\rm _{t}$ distribution","author":"tanaka","year":"1990","journal-title":"Symp VLSI Circuits Tech Dig"},{"key":"ref73","first-page":"240","article-title":"A 48nm 32Gb 8-level NAND flash memory with 5.5MB\/s program throughput","author":"chang","year":"2009","journal-title":"Proc ISSCC"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9431-5_1"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.1990.66097"},{"key":"ref70","first-page":"1","article-title":"A 1.8 V 2 Gb NAND flash memory for mass storage applications","author":"lee","year":"2003","journal-title":"Proc ISSCC"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/4.881212"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/5.622505"},{"key":"ref74","first-page":"242","article-title":"A 113mm $^{2}~32$ Gb 3b\/cell NAND flash memory","author":"futatsuyama","year":"2009","journal-title":"Proc ISSCC"},{"key":"ref75","first-page":"202","article-title":"A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS","author":"kim","year":"2011","journal-title":"Proc ISSCC"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2003.811702"},{"key":"ref79","doi-asserted-by":"crossref","DOI":"10.1017\/CBO9781139195065","author":"taur","year":"2009","journal-title":"Fundamentals of Modern VLSI Devices"},{"key":"ref60","first-page":"46","article-title":"An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology","author":"byeon","year":"2005","journal-title":"Proc ISSCC"},{"key":"ref62","article-title":"Non-volatile multilevel memory cell programming","author":"moschiano","year":"2010"},{"key":"ref61","first-page":"444","article-title":"A 3bit\/cell 32Gb NAND flash memory at 34nm with 6MB\/s program throughput and with dynamic 2b\/cell blocks configuration mode for a program throughput increase up to 13MB\/s","author":"marotta","year":"2010","journal-title":"Proc ISSCC"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2011.5784588"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243825"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2414711"},{"key":"ref66","first-page":"506","article-title":"A 16Gb 3b\/ Cell NAND flash memory in 56nm with 8MB\/s write rate","author":"li","year":"2008","journal-title":"Proc ISSCC"},{"key":"ref67","first-page":"246","article-title":"A 5.6MB\/s 64Gb 4b\/Cell NAND flash memory in 43nm CMOS","author":"trinh","year":"2009","journal-title":"Proc ISSCC"},{"key":"ref68","first-page":"446","article-title":"A 32-Gb MLC NAND flash memory with Vth endurance enhancing schemes in 32 nm CMOS","author":"lee","year":"2010","journal-title":"Proc ISSCC"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1988.663666"},{"key":"ref197","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2012.6213682"},{"key":"ref198","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2012.6213656"},{"key":"ref199","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2013.2283274"},{"key":"ref193","first-page":"196","article-title":"A 512 Gb 3 b\/cell flash memory on 64-word-line-layer BICS technology","author":"yamashita","year":"2017","journal-title":"Proc ISSCC"},{"key":"ref194","first-page":"202","article-title":"A 512 Gb 3 b\/cell 64-stacked WL 3D V-NAND flash memory","author":"kim","year":"2017","journal-title":"Proc ISSCC"},{"key":"ref195","first-page":"40","article-title":"MOVPE In $_{\\mathrm{ 1-x}}$ GaxAs high mobility channel for 3-D NAND memory","author":"capogreco","year":"2015","journal-title":"IEDM Tech Dig"},{"key":"ref196","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6478961"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2007.4339707"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1002\/9781119132639"},{"key":"ref190","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409636"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2015.7150307"},{"key":"ref191","first-page":"334","article-title":"Three-dimensional 128 Gb MLC vertical NAND flash-memory with 24-WL stacked layers and 50 MB\/s high-speed programming","author":"park","year":"2014","journal-title":"Proc ISSCC"},{"key":"ref92","first-page":"2e.1.1","article-title":"Scaling and reliability of NAND flash devices","author":"park","year":"2014","journal-title":"Proc IRPS"},{"key":"ref192","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417941"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2010.09.005"},{"key":"ref90","article-title":"Optimized client computing with dynamic write acceleration","author":"glen","year":"2014"},{"key":"ref98","first-page":"199","article-title":"A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies","author":"hwang","year":"2011","journal-title":"IEDM Tech Dig"},{"key":"ref99","first-page":"102","article-title":"25nm 64Gb MLC NAND technology and scaling challenges","author":"prall","year":"2010","journal-title":"IEDM Tech Dig"},{"key":"ref96","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.2007.375063"},{"key":"ref97","first-page":"125","article-title":"32nm 3-bit 32Gb NAND flash memory with DPT (double patterning technology) process for mass production","author":"park","year":"2010","journal-title":"Symp VLSI Tech Dig"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409666"},{"key":"ref81","first-page":"1","article-title":"A semiconductor memory development and manufacturing perspective","author":"atwood","year":"2014","journal-title":"Proc ESSCIRC"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2002.1010143"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/MSST.2013.6558421"},{"key":"ref80","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493863"},{"key":"ref89","year":"2015","journal-title":"M510DC 2 5-Inch TGC Enterprise SATA NAND Flash SSD Product Data Sheet"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9431-5_2"},{"key":"ref86","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-007-5146-0_9"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1109\/MSST.2010.5496985"},{"key":"ref88","year":"2012","journal-title":"P420m 2 5-Inch PCIe NAND Flash SSD Product Data Sheet"},{"key":"ref200","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2012.04.013"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409700"},{"key":"ref100","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2014.2377774"},{"key":"ref201","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2010.5488387"},{"key":"ref202","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2159010"},{"key":"ref127","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2015.7324754"},{"key":"ref126","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2327149"},{"key":"ref125","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2327661"},{"key":"ref124","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2013.6531977"},{"key":"ref129","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevLett.52.228"},{"key":"ref128","doi-asserted-by":"publisher","DOI":"10.1063\/1.1721637"},{"key":"ref130","doi-asserted-by":"publisher","DOI":"10.1080\/00018738900101122"},{"key":"ref133","doi-asserted-by":"publisher","DOI":"10.1109\/16.293343"},{"key":"ref134","doi-asserted-by":"publisher","DOI":"10.1109\/16.333823"},{"key":"ref131","doi-asserted-by":"publisher","DOI":"10.1109\/55.46938"},{"key":"ref132","doi-asserted-by":"publisher","DOI":"10.1063\/1.347116"},{"key":"ref136","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346821"},{"key":"ref135","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705335"},{"key":"ref138","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.47.2598"},{"key":"ref137","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2007.369864"},{"key":"ref139","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2009.5173283"},{"key":"ref140","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2009.5166255"},{"key":"ref141","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703437"},{"key":"ref142","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131570"},{"key":"ref143","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2012.2202910"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1063\/1.4906208"},{"key":"ref144","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2012.2203412"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"552","DOI":"10.1109\/IEDM.1987.191485","article-title":"new ultra high density eprom and flash eeprom with nand structure cell","author":"masuoka","year":"1987","journal-title":"1987 International Electron Devices Meeting"},{"key":"ref145","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2164543"},{"key":"ref109","first-page":"705","article-title":"Three-dimensional ‘atomistic’ simulation of discrete random dopant distribution effects in sub- $0.1~\\mu \\text{m}$ MOSFET’s","author":"wong","year":"1993","journal-title":"IEDM Tech Dig"},{"key":"ref108","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2024031"},{"key":"ref107","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409699"},{"key":"ref106","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2550660"},{"key":"ref105","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2010.2069082"},{"key":"ref104","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2010.2066253"},{"key":"ref103","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796826"},{"key":"ref102","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418892"},{"key":"ref111","doi-asserted-by":"publisher","DOI":"10.1016\/S0026-2714(01)00138-X"},{"key":"ref112","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.815862"},{"key":"ref110","doi-asserted-by":"publisher","DOI":"10.1109\/43.806802"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2000.904429"},{"key":"ref11","first-page":"326","article-title":"A 128Gb MLC NAND-flash device using 16 nm planar cell","author":"helm","year":"2014","journal-title":"Proc ISSCC"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1988.32843"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572587"},{"key":"ref14","first-page":"218","article-title":"A 128Gb 3b\/cell NAND flash design using 20 nm planar-cell technology","author":"naso","year":"2013","journal-title":"Proc ISSCC"},{"key":"ref15","first-page":"328","article-title":"A 93.4 mm $^{2}~64$ Gb MLC NAND-flash memory with 16 nm CMOS technology","author":"choi","year":"2014","journal-title":"Proc ISSCC"},{"key":"ref16","first-page":"31","article-title":"A new programming disturbance phenomenon in NAND flash memory by source\/drain hot-electrons generated by GIDL current","author":"lee","year":"2006","journal-title":"Proc Non-Volatile Semiconductor Memory Workshop"},{"key":"ref118","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346819"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1533\/9780857098092.1.75"},{"key":"ref117","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2175399"},{"key":"ref18","author":"richter","year":"2013","journal-title":"Flash Memories Economic Principles of Performance Cost and Reliability Optimization"},{"key":"ref19","first-page":"1","article-title":"A 125 mm $^{2}~1$ Gb NAND flash memory with 10 MB\/s program throughput","author":"nakamura","year":"2002","journal-title":"Proc ISSCC"},{"key":"ref119","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418893"},{"key":"ref114","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.2008.4558954"},{"key":"ref113","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.885683"},{"key":"ref116","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2011.5873216"},{"key":"ref115","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796827"},{"key":"ref120","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.910605"},{"key":"ref121","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2012.6241841"},{"key":"ref122","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2250477"},{"key":"ref123","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2004.836721"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5\/8013039\/07888451.pdf?arnumber=7888451","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T17:03:05Z","timestamp":1642006985000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7888451\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":202,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jproc.2017.2665781","relation":{},"ISSN":["0018-9219","1558-2256"],"issn-type":[{"value":"0018-9219","type":"print"},{"value":"1558-2256","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,9]]}}}