{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,16]],"date-time":"2026-05-16T09:20:40Z","timestamp":1778923240938,"version":"3.51.4"},"reference-count":83,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2017,9,1]],"date-time":"2017-09-01T00:00:00Z","timestamp":1504224000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1109\/jproc.2017.2697000","type":"journal-article","created":{"date-parts":[[2017,5,22]],"date-time":"2017-05-22T21:00:14Z","timestamp":1495486814000},"page":"1634-1649","source":"Crossref","is-referenced-by-count":107,"title":["Array Architectures for 3-D NAND Flash Memories"],"prefix":"10.1109","volume":"105","author":[{"given":"Rino","family":"Micheloni","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seiichi","family":"Aritome","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Crippa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582120"},{"key":"ref72","first-page":"1","article-title":"Inherent issues and challenges of program disturbance of 3D NAND flash cell","author":"shim","year":"2012","journal-title":"Proc 4th IEEE Int Memory Workshop (IMW)"},{"key":"ref71","first-page":"5.6.1","article-title":"Study of fast initial charge loss and it’s impact on the programmed states Vt distribution of charge-trapping NAND flash","author":"chen","year":"2010","journal-title":"IEDM Tech Dig"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417947"},{"key":"ref76","first-page":"202","article-title":"A 512 Gb 3b\/cell 64-stacked WL 3D V-NAND flash memory","author":"kim","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref77","first-page":"196","article-title":"A 512 Gb 3b\/cell Flash Memory on 64-Word-Line-Layer BiCS Technology","author":"yamashita","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref74","first-page":"334","article-title":"Three-dimensional 128 Gb MLC vertical NAND flash memory with 24-WL stacked layers and 50 MB\/s high-speed programming","author":"park","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref39","article-title":"7.2 A 128Gb 3b\/cell V-NAND flash memory with 1Gb\/s I\/O rate","volume":"51","author":"im","year":"2016","journal-title":"J Solid-State Circuits"},{"key":"ref75","article-title":"Scaling challenges beyond 1Xnm DRAM and NAND flash","author":"aritome","year":"2012","journal-title":"Proc Joint Rump Session VLSI Symp"},{"key":"ref38","first-page":"130","article-title":"A 128 Gb 3b\/cell V-NAND flash memory with 1 Gb\/s I\/O rate","author":"im","year":"2015","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2010.5556199"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2007.378899"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757458"},{"key":"ref32","article-title":"Ushering in the 3D memory era with V-NAND","author":"elliott","year":"2013","journal-title":"Proc Flash Memory Summit"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2010.5556216"},{"key":"ref30","first-page":"192","article-title":"Vertical cell array using TCAT(terabit cell array transistor) technology for ultra high density NAND flash memory","author":"jang","year":"2009","journal-title":"Proc IEEE Symp VLSI Technol"},{"key":"ref37","first-page":"95","article-title":"Inherent issues and challenges of program disturbance of 3D NAND flash cell","author":"shim","year":"2012","journal-title":"Proc IEEE Int Memory Workshop"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479011"},{"key":"ref35","first-page":"27","article-title":"A world’s first product of three-dimensional vertical NAND flash memory and beyond","author":"park","year":"2014","journal-title":"Proc NVMTS"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2352293"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757458"},{"key":"ref62","first-page":"27","article-title":"A world’s first product of three-dimensional vertical NAND flash memory and beyond","author":"park","year":"2014","journal-title":"Proc NVMTS"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2352293"},{"key":"ref63","first-page":"1","article-title":"A new cell-type string select transistor in NAND flash memories for under 20 nm node","author":"lee","year":"2012","journal-title":"Proc 4th IEEE Int Memory Workshop (IMW)"},{"key":"ref28","first-page":"122","article-title":"Novel 3-D structure for ultra high density flash memory with VRAT (vertical-recess-array-transistor) and PIPE (planarized integration on the same plane)","author":"kim","year":"2008","journal-title":"Proc IEEE Symp VLSI Technol"},{"key":"ref64","first-page":"130","article-title":"A 128 Gb 3b\/cell V-NAND flash memory with 1 Gb\/s I\/O rate","author":"im","year":"2015","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref27","first-page":"136","article-title":"Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices","author":"katsumata","year":"2009","journal-title":"Proc Symp VLSI Technol"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479011"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2016.7495285"},{"key":"ref29","first-page":"186","article-title":"Novel vertical-stacked-array-transistor (VSAT) for ultra-high-density and cost-effective NAND flash memory devices and SSD (solid state drive)","author":"kim","year":"2009","journal-title":"Proc IEEE Symp VLSI Technol"},{"key":"ref67","author":"aritome","year":"0","journal-title":"Patent 8891306"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2352293"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062960"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9431-5"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"552","DOI":"10.1109\/IEDM.1987.191485","article-title":"new ultra high density eprom and flash eeprom with nand structure cell","author":"masuoka","year":"1987","journal-title":"1987 International Electron Devices Meeting"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2009.5090581"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2013.6658450"},{"key":"ref21","first-page":"84","article-title":"Control gate length, spacing and stacked layers number design for 3D-stackable NAND flash memory2","author":"yanagihara","year":"2012","journal-title":"Proc IEEE IMW"},{"key":"ref24","first-page":"851","article-title":"Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device","author":"komori","year":"2008","journal-title":"IEDM Tech Dig"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2010.5488917"},{"key":"ref26","first-page":"22","article-title":"Multi-stacked 1G cell\/layer pipe-shaped BiCS flash memory","author":"maeda","year":"2009","journal-title":"VLSI Circuits Symp Dig"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424261"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2011.5873206"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2013.2247606"},{"key":"ref59","doi-asserted-by":"crossref","DOI":"10.1007\/978-94-007-5146-0","author":"micheloni","year":"2013","journal-title":"Inside Solid State Drives (SSDs)"},{"key":"ref58","first-page":"851","article-title":"Disturbless flash memory due to high boost efficiency on BiCS structure and optimal memory film stack for ultra high density storage device","author":"komori","year":"2008","journal-title":"IEDM Tech Dig"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409618"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9431-5"},{"key":"ref55","first-page":"142","article-title":"A 768 Gb 3 b\/cell 3D-floating-gate NAND flash memory","author":"tanaka","year":"2016","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref54","first-page":"3.3.1","article-title":"A floating gate based 3D NAND technology with CMOS under array","author":"parat","year":"2015","journal-title":"IEDM Tech Dig"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2012.2200682"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2011.5873208"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346903"},{"key":"ref11","year":"2014"},{"key":"ref40","first-page":"130","article-title":"256 Gb 3b\/Cell V-NAND flash memory with 48 stacked WL layers","author":"kang","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1533\/9780857098092.1.75"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14752-4_7"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2007.4339708"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418970"},{"key":"ref82","first-page":"3.1.1","article-title":"MOVPE In1-xGaxAs high mobility channel for 3-D NAND memory","author":"capogreco","year":"2015","journal-title":"IEDM Tech Dig"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424261"},{"key":"ref81","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2016.7495277"},{"key":"ref17","first-page":"22","article-title":"Multi-stacked 1G cell\/layer pipe-shaped BiCS flash memory","author":"maeda","year":"2009","journal-title":"VLSI Circuits Symp Tech Dig"},{"key":"ref18","first-page":"136","article-title":"Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices","author":"katsumata","year":"2009","journal-title":"Proc Symp VLSI Technol"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2014.6894346"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4418970"},{"key":"ref80","article-title":"Impact of discrete trapping in high pressure deuterium annealed and doped poly-Si channel 3D NAND macaroni","year":"2017","journal-title":"Proc IEEE Int Rel Phys Symp (IRPS)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705335"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/16.333844"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1002\/9781119132639"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.2003230"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9431-5"},{"key":"ref7","article-title":"3D flash memories","author":"aritome","year":"2011","journal-title":"Proc Int Memory Workshop"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14752-4_7"},{"key":"ref9","first-page":"1","article-title":"Three dimensionally stacked NAND flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30 nm node","author":"jung","year":"2006","journal-title":"IEDM Tech Dig"},{"key":"ref46","first-page":"668","article-title":"Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application","author":"whang","year":"2010","journal-title":"IEDM Tech Dig"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2160642"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1533\/9780857098092.1.75"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242440"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.809429"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2001.979396"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2010.5488392"},{"key":"ref43","first-page":"17","article-title":"Floating channel type SGT flash memory","volume":"2","author":"endoh","year":"1999","journal-title":"Proc Joint Int Meeting"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5\/8013039\/07932448.pdf?arnumber=7932448","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T17:03:06Z","timestamp":1642006986000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7932448\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9]]},"references-count":83,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jproc.2017.2697000","relation":{},"ISSN":["0018-9219","1558-2256"],"issn-type":[{"value":"0018-9219","type":"print"},{"value":"1558-2256","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,9]]}}}