{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,9]],"date-time":"2026-04-09T14:33:40Z","timestamp":1775745220459,"version":"3.50.1"},"reference-count":154,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Proc. IEEE"],"published-print":{"date-parts":[[2020,8]]},"DOI":"10.1109\/jproc.2019.2950173","type":"journal-article","created":{"date-parts":[[2019,11,27]],"date-time":"2019-11-27T22:03:12Z","timestamp":1574892192000},"page":"1283-1302","source":"Crossref","is-referenced-by-count":63,"title":["Large-Scale Field-Programmable Analog Arrays"],"prefix":"10.1109","volume":"108","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6866-3156","authenticated-orcid":false,"given":"Jennifer","family":"Hasler","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378248"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2211049"},{"key":"ref33","first-page":"2244","article-title":"Integrated floating-gate programming environment for system-level ICs","volume":"24","author":"kim","year":"2016","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2015.7085484"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2737095.2737107"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2013.6674625"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2194847"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2056832"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320937"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2613080"},{"key":"ref28","first-page":"177","article-title":"An OTA-based large-scale field programmable analog array (FPAA) for faster on-chip communication and computation","author":"twigg","year":"2007","journal-title":"Proc IEEE ISCAS"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124550"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/j.dsp.2007.09.013"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea7030017"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1049\/el:19920017"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea9010004"},{"key":"ref24","first-page":"296","article-title":"A flexible 2-D switched-capacitor FPAA architecture and its mapping algorithm","volume":"1","author":"koneru","year":"1999","journal-title":"Proc of Midwest-CAS"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.1996.594074"},{"key":"ref101","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2017.7945073"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2543729"},{"key":"ref100","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2386773"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.858618"},{"key":"ref50","year":"2011","journal-title":"PSoC5 Data Sheet"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/258305.258329"},{"key":"ref154","article-title":"A system design approach to neuromorphic classifiers","author":"ramakrishnan","year":"2013"},{"key":"ref153","doi-asserted-by":"publisher","DOI":"10.1109\/TLT.2009.43"},{"key":"ref150","doi-asserted-by":"publisher","DOI":"10.1109\/TLT.2009.33"},{"key":"ref152","doi-asserted-by":"publisher","DOI":"10.1109\/TLT.2009.30"},{"key":"ref151","doi-asserted-by":"publisher","DOI":"10.1109\/TLT.2009.51"},{"key":"ref146","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2015.7160011"},{"key":"ref147","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351322"},{"key":"ref148","doi-asserted-by":"publisher","DOI":"10.3991\/ijoe.v10i6.3997"},{"key":"ref149","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.921607"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1967.tb01738.x"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2290305"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5118220"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164295"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/4.982418"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/92.920839"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/24.914547"},{"key":"ref52","first-page":"1","article-title":"10 MHz field programmable analog array prototype based on CMOS current conveyors","author":"gaudet","year":"1999","journal-title":"Proceedings of the MICRO"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2165755"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"382","DOI":"10.1109\/T-ED.1972.17428","article-title":"current-voltage characteristics of small size mos transistors","volume":"19","author":"hoeneisen","year":"1972","journal-title":"IEEE Transactions on Electron Devices"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/0038-1101(72)90103-7"},{"key":"ref6","author":"mead","year":"1989","journal-title":"Analog VLSI and Neural Systems"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2009.4907384"},{"key":"ref8","article-title":"Analog’s answer to FPGA opens field to masses","author":"bains","year":"2008","journal-title":"EE Times"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea6030013"},{"key":"ref7","first-page":"817","article-title":"Single transistor learning synapses","author":"hasler","year":"1994","journal-title":"Advances in Neural Information Processing Systems 7"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-46117-5_45"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/2617593"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5117736"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.112130359"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2013.2282616"},{"key":"ref42","first-page":"i.1092","article-title":"A continuous-time field programmable analog array (FPAA) consisting of digitally reconfigurable $\\text{G}_{M}$\n-cells","author":"becker","year":"2004","journal-title":"Proc ISCAS"},{"key":"ref41","first-page":"651","article-title":"A 531 nW\/MHz, $128\\times32$\n current-mode programmable analog vector-matrix multiplier with over two decades of linearity","author":"chawla","year":"2004","journal-title":"Proc CICC"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005697"},{"key":"ref43","first-page":"595","article-title":"A continuous-time hexagonal field-programmable analog array in 0.13 $\\mu\\text{m}$\n CMOS with 186 MHz GBW","author":"becker","year":"2008","journal-title":"Proc IEEE ISSCC"},{"key":"ref127","doi-asserted-by":"publisher","DOI":"10.1109\/5.293155"},{"key":"ref126","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2710020"},{"key":"ref125","article-title":"ICESTUDIO: An open source graphical FPGA tool","author":"evenchick","year":"2016","journal-title":"HACKADAY"},{"key":"ref124","author":"wadge","year":"1985","journal-title":"Lucid the Dataflow Programming Language"},{"key":"ref73","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2002.1187157"},{"key":"ref72","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.887473"},{"key":"ref129","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2013.6732259"},{"key":"ref71","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.895390"},{"key":"ref128","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645593"},{"key":"ref70","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.918006"},{"key":"ref76","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2005.854488"},{"key":"ref130","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2280295"},{"key":"ref77","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2005.844336"},{"key":"ref74","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1466045"},{"key":"ref75","first-page":"213","article-title":"A 0.5 $\\mu\\text{m}$\n CMOS programmable discrete-time $\\Delta$\n-$\\Sigma$\n modulator with floating gate elements","volume":"1","author":"pereira","year":"2004","journal-title":"Proc ISCAS"},{"key":"ref133","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527525"},{"key":"ref134","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea6030014"},{"key":"ref131","doi-asserted-by":"publisher","DOI":"10.1109\/EWME.2016.7496458"},{"key":"ref78","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864115"},{"key":"ref132","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5536992"},{"key":"ref79","doi-asserted-by":"publisher","DOI":"10.1109\/IWSOC.2005.83"},{"key":"ref136","author":"park","year":"2006","journal-title":"Remote FPGA reconfiguration using MicroBlaze or PowerPC processors"},{"key":"ref135","author":"kurose","year":"2010","journal-title":"Computer Networking A Top-down Approach"},{"key":"ref138","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2013.6732330"},{"key":"ref137","author":"kuramoto","year":"2014","journal-title":"QuickBoot method for FPGA design remote update"},{"key":"ref60","author":"gilder","year":"2005","journal-title":"The Silicon Eye"},{"key":"ref139","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2005.1559549"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/55.75728"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.1989.118698"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2013.00118"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1999.780744"},{"key":"ref140","doi-asserted-by":"publisher","DOI":"10.7227\/IJEEE.50.2.7"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2716338"},{"key":"ref141","doi-asserted-by":"publisher","DOI":"10.1145\/3126594.3126618"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.889365"},{"key":"ref142","doi-asserted-by":"publisher","DOI":"10.3182\/20090210-3-CZ-4002.00038"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.925351"},{"key":"ref143","year":"2018","journal-title":"AnadigmDesigner2 EDA Software"},{"key":"ref68","article-title":"A fine-grain FPAA fabric for RF + baseband","author":"hasler","year":"2015","journal-title":"Proc GOMAC"},{"key":"ref144","doi-asserted-by":"publisher","DOI":"10.1109\/TE.2008.916762"},{"key":"ref2","first-page":"114","article-title":"Cramming more components onto integrated circuits","volume":"38","author":"moore","year":"1965","journal-title":"Electronics"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2005.1594042"},{"key":"ref145","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2011.5937090"},{"key":"ref1","author":"mead","year":"1980","journal-title":"Introduction to VLSI Design"},{"key":"ref109","doi-asserted-by":"publisher","DOI":"10.1109\/ARVLSI.2001.915559"},{"key":"ref95","doi-asserted-by":"publisher","DOI":"10.1109\/ICSMC.2011.6084222"},{"key":"ref108","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1999.808584"},{"key":"ref94","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2011.5963964"},{"key":"ref107","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1999.745213"},{"key":"ref93","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2297056"},{"key":"ref106","year":"2012","journal-title":"Scilab Free and Open Source Software for Numerical Computation"},{"key":"ref92","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050755"},{"key":"ref105","year":"2019"},{"key":"ref91","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2017.2777784"},{"key":"ref104","year":"2012","journal-title":"SoC FPGAs Integration to Reduce Power Cost and Board Size"},{"key":"ref90","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2017.2771392"},{"key":"ref103","year":"2012","journal-title":"Zynq All Programmable SoC Architecture"},{"key":"ref102","year":"2019"},{"key":"ref111","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.818374"},{"key":"ref112","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050528"},{"key":"ref110","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378373"},{"key":"ref98","article-title":"Real-time vital-sign monitoring in the physical domain on a mixed-signal reconfigurable platform","author":"toreyin","year":"0","journal-title":"IEEE Trans Biomed Circuits Syst"},{"key":"ref99","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea8020017"},{"key":"ref96","doi-asserted-by":"publisher","DOI":"10.1109\/EMBC.2016.7591797"},{"key":"ref97","doi-asserted-by":"publisher","DOI":"10.1109\/ICSENS.2016.7808748"},{"key":"ref10","article-title":"A reconfigurable general purpose analog integrated circuit","author":"brooke","year":"1988"},{"key":"ref11","article-title":"Wiring considerations in analog VLSI systems, with application to field-programmable networks","author":"sivilotti","year":"1991"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.104162"},{"key":"ref13","first-page":"169","article-title":"The EPAC architecture: An expert cell approach to field programmable analog circuits","volume":"1","author":"klein","year":"1992","journal-title":"Proc of Midwest-CAS"},{"key":"ref14","article-title":"Anadigm: Specifically generic analog functions for FPAAs Anadigm says","year":"2004","journal-title":"EE Times"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/5.58356"},{"key":"ref118","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea6010003"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2504119"},{"key":"ref82","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2245351"},{"key":"ref117","year":"1999","journal-title":"Barcelona Design"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3320288.3320304"},{"key":"ref81","first-page":"860","article-title":"Analog VLSI implementation of support vector machine learning and classification","author":"peng","year":"2008","journal-title":"Proc ISCAS"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2016.7738680"},{"key":"ref84","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.853401"},{"key":"ref119","article-title":"Simulink framework for design to and automated conversion on large-scale FPAA devices","author":"schlottmann","year":"0","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea8040047"},{"key":"ref83","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.846663"},{"key":"ref114","first-page":"613","article-title":"Leveraging designer’s intent: A path toward simpler analog CAD tools","author":"kim","year":"2009","journal-title":"Proc IEEE CICC"},{"key":"ref113","doi-asserted-by":"publisher","DOI":"10.1109\/43.68402"},{"key":"ref116","doi-asserted-by":"publisher","DOI":"10.1016\/j.jala.2006.07.012"},{"key":"ref80","first-page":"13","article-title":"An analog programmable multi-dimensional radial basis function based classifier","author":"peng","year":"2007","journal-title":"Proc IFIP Int Conf Very Large-Scale Integr"},{"key":"ref115","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2332265"},{"key":"ref120","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-016-0914-y"},{"key":"ref89","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea7030021"},{"key":"ref121","doi-asserted-by":"publisher","DOI":"10.1109\/MPRV.2007.41"},{"key":"ref122","article-title":"Visual programming languages: A survey","author":"boshernitsan","year":"2004"},{"key":"ref123","doi-asserted-by":"publisher","DOI":"10.1145\/1013208.1013209"},{"key":"ref85","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea3020073"},{"key":"ref86","year":"0","journal-title":"OpenMSP430 Project Open Core MSP430"},{"key":"ref87","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2280718"},{"key":"ref88","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2773399"}],"container-title":["Proceedings of the IEEE"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/5\/9143211\/08915721.pdf?arnumber=8915721","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T13:39:54Z","timestamp":1651066794000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8915721\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8]]},"references-count":154,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/jproc.2019.2950173","relation":{},"ISSN":["0018-9219","1558-2256"],"issn-type":[{"value":"0018-9219","type":"print"},{"value":"1558-2256","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,8]]}}}