{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T16:33:36Z","timestamp":1694622816117},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[1986,1,1]],"date-time":"1986-01-01T00:00:00Z","timestamp":504921600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Select. Areas Commun."],"published-print":{"date-parts":[[1986,1]]},"DOI":"10.1109\/jsac.1986.1146294","type":"journal-article","created":{"date-parts":[[2004,4,29]],"date-time":"2004-04-29T00:28:59Z","timestamp":1083198539000},"page":"39-48","source":"Crossref","is-referenced-by-count":8,"title":["Design and VLSI Implementation of a Concurrent Solver for N-Coupled Least-Squares Fitting Problems"],"prefix":"10.1109","volume":"4","author":[{"given":"K.","family":"Jainandunsing","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Deprettere","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Hierarchical iterative flowgraph integration for VLSI array processors","author":"kung","year":"1984","journal-title":"Proc USC Workshop on VLSI and Signal Processing"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1117\/12.944009"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/0022-247X(79)90124-0"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1959.5222693"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1983.1172177"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1984.1172772"},{"key":"ref16","first-page":"65","article-title":"Let's design algorithms for VLSI systems","author":"kung","year":"1979","journal-title":"Proc First Caltech Conf VLSI"},{"key":"ref17","article-title":"VLSI array architectures for matrix factorization","author":"ahmed","year":"1981","journal-title":"Workshop on Fast Algorithms for Linear Systems"},{"key":"ref18","author":"kung","year":"0","journal-title":"VLSI pipelined array processors for image processing"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1983.1164051"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653825"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1984.1056966"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1985.1168154"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1984.1172772"},{"key":"ref7","author":"dewilde","year":"1985","journal-title":"VLSI and Modern Signal Processing"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653828"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1983.1164236"},{"key":"ref9","article-title":"On supercomputing with systolic\/wavefront array processors","volume":"72","author":"kung","year":"1984","journal-title":"Proc IEEE"}],"container-title":["IEEE Journal on Selected Areas in Communications"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx6\/49\/25818\/01146294.pdf?arnumber=1146294","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:25:57Z","timestamp":1638217557000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1146294\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1986,1]]},"references-count":18,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1986,1]]}},"URL":"https:\/\/doi.org\/10.1109\/jsac.1986.1146294","relation":{},"ISSN":["0733-8716"],"issn-type":[{"value":"0733-8716","type":"print"}],"subject":[],"published":{"date-parts":[[1986,1]]}}}